The new standard (JESD229-2) has been released by the JEDEC Solid State Technology Association and can be downloaded free of charge.

Wide I/O 2 provides four times the memory bandwidth (up to 68GBps) of the previous version of the standard, but at lower power consumption (better bandwidth/Watt) with the change to 1.1V supply voltage. From a packaging standpoint, the Wide I/O 2 die is optimized to stack on top of a system on chip (SOC) to minimize power consumption and footprint.

Hung Vuong, Chairman of the JC-42.6 Subcommittee for Low Power Memories, noted, "Wide I/O 2 mobile DRAM is an extension of the breakthrough technology pioneered with the publication of Wide I/O in 2012." Just as switching to multicore processors significantly increased overall computer speed without the need to jump to a new process node, so the vertically stacked architecture allows the Wide I/O 2 interface to deliver four times the bandwidth of LPDDR4 DRAM for around one quarter of the I/O speed.

"With the recent publication of LPDDR4, these two new standards from JEDEC offer designers a range of mobile memory solutions, allowing for maximum flexibility," Vuong said. "Designers working with a horizontal architecture can choose LPDDR4, while those working with a vertical architecture are supported by Wide I/O 2. In either case, the committee worked to deliver the memory performance that the market requires."

Last week, SK hynix announced the development of Wide IO2 mobile DRAM chip that is four times faster than the existing Low Power DDR4 (LPDDR4).

Key specifications:

• Number of channels: 4 and 8
• Number of banks: 32 per die
• Density: 8 Gb to 32 Gb
• Page size: 4 KB (4-channel die), 2 KB (8-channel die)
• Max bandwidth per die: 34 GB/s (4-channel die) & 68 GB/s (8-channel die) respectively
• Max I/O speed: 1066 Mbps, 800 Mbps & 1066 Mbps speed bin defined
• Operating Supply Voltage: 1.1V