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Tuesday, December 11, 2012
 Intel Focuses On Smaller, System-On-Chips For Mobile Devices
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Message Text: Intel on Monday said it is putting more emphasis now on system-on-a-chip technology, which is used widely in smartphones and tablets, where the company has largely been absent.

At the International Electron Devices conference in San Francisco on Monday, Intel reported on the progress of its technology for 22nm SoCs, saying that the technology will be ready for high volume manufacturing in 2013.

Mark Bohr, head of Intel's process technology development group, said Intel?s 22-nm FinFET process is cost effective, contradicting report it is 30 to 40 percent more expensive than TSMC's 28nm planar process.

Intel is applying its 22-nanometer "Tri-Gate" 3D chip technology to SoCs for the first time. Intel said its 22nm 3D process variation for SoCs outperforms its own 32nm planar process by 20 to 65 percent and covers four orders of magnitude in leakage current. Specifically, the 22nm process provides 51~56% improvements in high voltage performance used for fast interfaces such Ethernet, HDMI and PCI Express.

The new 22nm process supports high and standard performance options as well as low and ultra low power ones. It also includes SRAM designs optimized for density, power and performance some of which now hit 2.6 GHz at 1V, up from 1.8 GHz at 32 nm.

Intel's current mobile SoCs are manufactured at 32 nm. Those SoCs include the Clover Trail chip being used in Windows 8 tablets and the Medfield chips adopted for Motorola and Lenovo smartphones, among other devices. Intel's rival in the mobile chip market Qualcomm makes its top-end SoCs at 28 nm and Nvidia uses 40 nm technology.

Intel already makes PC processors at 22 nm, but SoCs pack more features onto one piece of silicon, making 22nm manufacturing more complicated.

According to current projections, 14nm wafers made with today?s 193-nm immersion lithography could be be significantly more expensive than 28nm parts. The next-generation lithography (EUV) would cut some costs as soon as the EUV lithography tools are ready by 2014, but still the new wafers are expected to me exoensive.

Commenting on the the cost of future 14nm wafers, Bohr said that although cost per wafer has always gone up each generation, the increase in transistor density at 14nm brings the cost per transistor down.

Seperately, IBM also talked about its 22-nm process. The company said it is prototyping server processors in a new 3-D ready, 22-nm process technology it hopes will deliver 25 to 35 percent boosts over its 32-nm chips, with server processors running up to 5.5 GHz and others with up to 80 Mbytes embedded DRAM.
 
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