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Tuesday, January 12, 2016
JEDEC Updates The High Bandwidth Memory (HBM) Standard


JEDEC Solid State Technology Association has updated the High Bandwidth Memory (HBM) DRAM standard to offer even more bandwidth.

HBM DRAM is used in Graphics, High Performance Computing, Server, Networking and Client applications where peak bandwidth, bandwidth per watt, and capacity per area are valued metrics to a solution's success in the market. The standard was developed and updated with support from GPU and CPU developers to extend the system bandwidth growth curve beyond levels supported by traditional discrete packaged memory.

The new JESD235A standard leverages Wide I/O and TSV technologies to support up to 8 GB per device at speeds up to 256 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. The standard supports 2-high, 4-high and 8-high TSV stacks of DRAM at full bandwidth to allow systems flexibility on capacity requirements from 1 GB - 8 GB per stack.

Additional improvements in the recent update include a new pseudo channel architecture to improve effective bandwidth, and clarifications and enhancements to the test features. JESD235A also defines a new feature to alert controllers when DRAM temperatures have exceeded a level considered acceptable for reliable operation so that the controller can take appropriate steps to return the system to normal operation.



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