Saturday, January 31, 2015
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
ASUS Announces The B85M-Gamer Mainboard
AT&T, Verizon Among Winners Of US Airwaves Auction
Apple Closes the Gap on Samsung Fourth Quarter's Worldwide Smartphone Shipments
Verizon To Let USers Opt Out Supercookies
Microsoft Outlines Windows 10 Options For The Enterprise
Jolla Tablet Returns to Indiegogo With A 64GB Version
BT Sees Ultrafast Broadband Not Coming Earlier Than 2025
Google To Change Privacy Policy After UK's Watchdog Investigation
Active Discussions
Why Double Logins ?
retrieving burned cd information
Writing Audio files on DVDs ?
Need major help with Gigabeat
New match-3 puzzle game launch now!
Rimage 2000i
Sound card for my Laptop
hello
 Home > News > Mobiles > Toshiba...
Last 7 Days News : SU MO TU WE TH FR SA All News

Friday, February 22, 2013
Toshiba Develops Low Power Technology for Embedded SRAM


Toshiba has developed an innovative low-power technology for embedded SRAM for application in smart phones and other mobile products.

The new technology reduces active and standby power in temperatures ranging from room temperature (RT) to high temperature (HT) by using a bit line power calculator (BLPC) and a digitally controllable retention circuit (DCRC). A prototype has been confirmed to reduce active and standby power consumption at 25C by 27% and 85%, respectively.

Typically, longer battery life requires lower power consumption in both high performance and low performance modes (MP3 decoding, background processing, etc.). As low performance applications require only tens of MHz operation, SRAM temperature remains around RT, where active and leakage power consumptions are comparable. Given this, the key issue is to reduce active and standby power from HT to RT.

Toshiba's new technology applies a BLPC and DCRC. The BLPC predicts power consumption of bit lines by using replicated bit lines to monitor the frequency of the ring oscillator. It minimizes the active power of the SRAM in certain conditions by monitoring the current consumption of the SRAM rest circuits. The DCRC decreases standby power in the retention circuit by periodically activating itself to update the size of the buffer of the retention driver.

Toshiba presented this development at the 2013 IEEE International Solid-State Circuit Conference in San Francisco, CA on February 20.


Previous
Next
PayPal Brings Mobile Payments To Europe        All News        OCZ Bundles Far Cry 3 PC Game With Its Vector SSD Series
Mobile World Congress Kicks Off On Monday     Mobiles News      Next LG Optimus G II To Use ARM-based Chips Developed In-house

Get RSS feed Easy Print E-Mail this Message

Related News
Compal To Take Over Toshiba's TV Business
Toshiba Reorganization to Strengthen IoT-Related Business
Toshiba Develops Cloud System for Instantaneous Remote Control of One Million Devices
Toshiba Launches NFC Built-in SDHC Memory Card
Toshiba Launches 3TB 2.5-inch HDD, Showcases First PCIe Single Package SSD
Toshiba Adds New Models To Click and Encore Families
Toshiba Develops Glasses-Free UHD 2D-3D Switching Display
IHI and Toshiba to Demo Ocean Current Power Generation System
Toshiba and SK Hynix Reach Settlement in Lawsuit Ahead Of CES
Toshiba Announces 6TB Enterprise Capacity HDD Models
Renesas Develops 16nm FinFET SRAM
Toshiba's New Canvio AeroCast Wireless HDD Lets You Play Digital Content On Your TV

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2015 - All rights reserved -
Privacy policy - Contact Us .