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Wednesday, November 28, 2012
BiTMICRO Reveals Talino Architecture for Enterprise SSDs


BitMicro has announced its next-generation SSD controller, the Talino ASIC, which represents an eight-fold increase in I/O random read-write performance over its existing architecture.

The company's Talino Quad Core ASIC controller integrates embedded processors with a high speed multi-bus design. BitMicro says a single Talino SSD controller can reach up to 400,000 random IOPS at 4KB and can perform up to 4,096 concurrent flash operations. To complete the architecture, the Talino controller connects with several of BiTMICRO's new ISIP ASICs.

By comparison, Hitachi Data Systems recently released its first enterprise SSD, a single 1.6TB module, which uses a 6Gbps SAS 2.0 interface. That drive can perform just over 1 million random read I/Os per second (IOPS) using 8K block sizes and 270,000 random write IOPS.

"One of the innovative attributes of the Talino architecture is its 'building block' design. A single Talino ASIC can connect to as many as 60 ISIP chips, each connecting to up to eight flash die," states Zophar Sante, VP of Marketing and Sales, "Multiple Talino ASICs can easily interconnect via a PCIe switch to create 1U, 2U and 3U complete storage systems with enormous capacities and blistering performance. These Talino based storage systems can use "off the shelf" front-end file systems that support FC, FCoE, iSCSI, NFS, CIFS, Ethernet and can also include volume management, virtualization and storage services software."

The Talino ASIC packs in even more features, with multiple high performance buses specifically built for flash memory, XOR RAID, power management features, AES-XTS encryption, end-to-end protection information, and full data path protection.

Interface controllers are built directly into the chip, with 8x 5Gb PCIe lanes, 2x 6Gb SAS ports and 2x 6Gb SATA ports. With two ISIP embedded directly into the controller, Talino can even be integrated in a single-tier architecture while incorporating ISIP?s features. ISIP itself includes hot plug support, RAID configuration support and BCH error correction code. The chip supports Legacy, Toggle 1.0 and ONFI 2.3 flash in single, dual, quad, and octal die packages.

BitMicro's initial maxIO product line, due out by the end of 2012, will use the Talino architecture and is expected to include PCIe, NVMe and SAS interfaces.


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