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Saturday, August 20, 2011
Intel Discloses New Architecture Features of Next Generation Itanium Processor Poulson

During the Hot Chips conference at Stanford University, Intel announced new architecture features of its upcoming Itanium processor, codenamed "Poulson."

New features such as the Intel Instruction Replay Technology, Intel Hyper-Threading Technology improvements and Itanium New Instructions are aimed to take full advantage of the next generation, 12-wide issue architecture.

Intel Instruction Replay Technology is a new capability that enables errant instructions to be re-issued and thereby automatically recover from severe errors to help prevent system crashes and data corruptions.

In addition, Poulson adds extensive RAS protection to nearly all the major structures in the Itanium core design. This includes the Last Level Cache (LLC), Mid-level Instruction cache (MLI), Mid-level Data cache (MLD), Integer Execution Unit (IEU) and Floating Point Unit (FPU), to name a few.

Intel Hyper-Threading Technology, enhanced with dual-domain multi-threading support - new architecture that enables independent front and backend pipeline execution to improve multi-thread efficiency and performance.

Major hardware investments on multi-threading include: dual threaded register files, dual threaded data side Translation buffers (TLBs), and a new fairness mechanism. Together, these additions enable the dual domain multi-threading support to significantly improve Poulson?s multi-threading performance over that of the previous generation.

Intel Itanium New Instructions -- new instructions simplify common tasks and branch operations to help take future Itanium performance to the next level.

The above features are ―designed to take full advantage of the 8-core, 12-wide issue architecture by enabling the maximum amount of parallel execution, said Pauline Nist, General Manager of Mission Critical Segment at Intel.

Additional Poulson Highlights:

- Eight high-capacity cores
- 54MB on-die memory (50MB SRAM)
- 3.1 billion transistors on 32nm process technology
- 33 percent higher system bandwidth improvement with higher bus speeds (QPI and SMI)
- Next-generation architecture with new data and instruction pipelines, floating-point pipeline and instruction buffers
- 2x max execution width vs. current architecture from 6- to 12-issue
- Advances in reliability, availability and serviceability (RAS) features
- Improved power management features and reduced overall socket power consumption
- Pin compatibility with the current Intel Itanium 9300 Processor Series

Intel says that "Poulson" will be the most sophisticated Intel processor to date, and is on track for launch in 2012.

It is followed by a future "Kittson" processor, currently under development.

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