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Matrix Takes 3D Memory To Gigabit Level ! - 5/11/2005 8:13:36 AM   

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Matrix Semiconductor introduced its third generation of one-time-programmable 3D memory on Tuesday, boasting a new architecture that has improved bit density by 23 percent.
The "segmented wordline" architecture of the new "Trinity" family of Matrix memories will help push the technology up to 128 Mbytes or a gigabit in size, enough for a new generation of portable devices with richer content, according to Dennis Segers, the company's chief executive.

In all, a 1-gigabit Trinity chip is roughly 10 percent smaller than a 512-Mbit Flagstaff part, the only hint that Segers would give as to the part's cost. While the unit cost of the chip isn't an issue for end users, it will determine the price that user pays for dedicated media, such as movies stored and distributed on the solid-state devices.

Once Matrix understood how the relationship between the support circuitry and the actual memory array, it paved the way to rearchitect the way in which they both are constructed, according to Segers. The segmented wordline architecture "hides" the vertical vias within the chip in between the memory arrays, instead of surrounding them in the "checkerboard" architecture used within the Matrix "Flagstaff" second-generation component.

The segmented wordline architecture is also the subject of the hundredth patent filed by Matrix, the company said.

The argument used to design the Matrix chips is that "when land cost is real expensive you build skyscrapers," Segers said, referring to what are usually "single story" components spread out within a package. The Matrix competition is from flash memory chips that are stacked to simulate the same three-dimensional structure, although Segers claims that the 31 sq. mm that the Trinity 1-gigabit die requires is roughly a quarter of the size of a flash chip fabricated at 90 nanometers.

Interestingly, the design of the new chip also allows it to be fabricated as a sort of module, with the control logic attached to the memory array using different processes. The first two generations of the Matrix cells used 0.25-micron and 0.15-micron processes, respectively, but the current generation can use 0.15-micron lines for the CMOS component and a 130-nm process for the memory array. Future generations are being designed with 140-nm processes for the CMOS logic and 90-nm lines for the CMOS array; "roughly a two to one ratio," according to Segers.

"It is an extension [of the previous technology], but by virtue of density and cost points, it can open up new applications that the previous family did not address," Segers said.

Source : ExtremeTech

Matrix 3D Memory Array
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