The International Society 2018 Symposia on VLSI Technology and Circuits kicks off this June and tech companies will present research results related state-of-the-art semiconductor and circuit technology, including advancements in the 10nm, 7nm and 3nm semicondutior processes and MRAM.
Held June 18-22, 2018 in Honolulu, HI, the event will host speakers from Samsung, Qualcomm, GLOBALFOUNDRIES, Imec and more.
Samsung will give the following intersting lectures:
- "True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM Cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break"
- "8LPP Logic Platform Technology for Cost‐Effective High Volume M
anufacturing"
- "Highly Manufacturable Low Power and High Performance 11LPP Platform Technology for Mobile and GPU Applications"
Samsung in February officially announced plans to begin commercial production of 7nm SoCs using the EUV lithography starting from the second half of this year.
The company has also talked about the "8LPP" (Low Power Plus) manufacturing process, which uses a combination of ArF immersion exposure and multi patterning techniques (deep ultraviolet lithography). The 8LPP fabrication technology is an evolution of Samsung's 10 nm node that uses narrower metal pitches and promises a 10% area reduction (at the same complexity) as well as a 10% lower power consumption (at the same frequency and complexity) compared to the 10LPP process.
In addition to Samsung, GLOBALFOUNDRIES will present: "A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications"
For its part, Qualcomm will talk about "High Performance Mobile SoC Productization with 2nd Generation 10nm FinFET Technology and
Extension to 8nm Scaling".
Imec will talk about CMOS transistor technology using a 3nm node "Enabling CMOS Scaling Towards 3nm and Beyond."
The paper "The Complementary FET (CFET) for CMOS Scaling Beyond N3" is a cooperative effort of Imec, GLOBALFOUNDRIES, Coventor and Tokyo Electron. And Samsung will talk about "Smart Scaling Tech. for Advanced FinFET Devices."
In the memory technology, companies will present their latest work on magnetoresistive memory (MRAM):
- Embedded STT‐MRAM in 28‐nm FDSOI Logic Process for Industrial MCU/IoT Application - Samsung
- 22‐nm FD‐SOI Embedded MRAM with Full Solder Reflow Compatibility and Enhanced Magnetic Immunity - Globalfoundries
- Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low
Switching Current and High Breakdown Voltage for STT‐MRAM at 10 nm and Beyond - Qualcomm Technologies, Inc, Applied Materials, Inc
- Demonstration of Ultra‐Low Voltage and Ultra Low Power STT‐MRAM Designed for Compatibility with
0x Node Embedded LLC Applications - TDK‐Headway Technologies
TSMC will also announce a 40nm 16Mb embedded perpendicular‐MRAM with
Hybrid‐Resistance reference, sub‐μA sensing resolution, and 17.5nS read access time.
A research group of Imec and ETH Zurich (Swiss Federal Institute of Technology Zurich) will report the results of a spin-orbit torque (SOT) system MRAM integrated in a the 300mm wafer for low power and ultrafast embedded memories.
Toshiba will report a technique to broaden the design margin of High‐speed Voltage Control Spintronics Memory (VoCSM). Here a spin-orbit torque (SOT) MRAM is compared with the spin torque (STT) MRAM. The voltage-torque MRAM has a higher density compared to the spin-orbit torque MRAM, but it is also faster and consumes less power.
Besides development in MRAM, a research group led by University of Michigan and includes ARM, AMD and Texas Instruments will talk about an energy ffficient Adiabatic FRAM with 0.99 pJ/bit Write for IoT
applications.
In addition, Fujitsu Laboratories will present a memory expansion technology for large‐scale data processing using software‐controlled SSD.