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Appeared on: Tuesday, February 25, 2014
Hybrid Memory Cube Consortium Releases of Second-Generation Specification

The Hybrid Memory Cube Consortium (HMCC), dedicated to the development of an interface specification for the Hybrid Memory Cube (HMC) technology, has developed of a new interface specification.

The HMCC also released a first draft of the new specification to consortium adopters that now numbers more than 120. The new specification supports increased data rate speeds advancing short-reach (SR) performance from 10 Gb/s, 12.5 Gb/s, and 15 Gb/s, up to 30 Gb/s. The new specification also migrates the associated channel model from SR to VSR to align with existing industry nomenclature. The ultra short-reach (USR) definition also increases performance from 10 Gb/s up to 15 Gb/s.

The HMCC, founded by memory providers Micron Technology, Samsung Electronics, and SK hynix, has begun circulating this draft specification to adopters, with the goal of incorporating adopter members' input and targeting a completion date of May 2014 for the final version. The first-generation specification was completed and released publicly in April 2013; several developer and adopter companies, including Altera, Xilinx, and Open-Silicon, have already begun leveraging the specification to design products and solutions that incorporate HMC technology.

HMC uses through-silicon vias (TSVs) - vertical conduits that electrically connect a stack of individual chips - to combine high-performance logic with dynamic random access memory (DRAM) die. The first commercial HMC implementation is sampling from Micron in a 2GB density with a 160 GB/s of memory bandwidth, while using up to 70 percent less energy per bit than existing technologies.

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