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Appeared on: Wednesday, February 20, 2013
GLOBALFOUNDRIES Offers 55nm CMOS Logic Process with ARM Memory and Logic IP Support for Low Voltage

GLOBALFOUNDRIES today announced additional enhancements to the foundry's 55-nanometer (nm) Low-Power Enhanced (LPe) process technology platform - 55nm LPe 1V - with next-generation memory and logic IP solutions from ARM.

The 55nm LPe 1V is the first enhanced process node to support ARM's 1.0/1.2V physical IP library, enabling chip designers to use a single process that supports two operating voltages in a single SoC.

"The key advantage of this 55nm LPe 1V offering is that the same design libraries can be used whether you are designing at 1.0 voltage or 1.2 voltage power option," said Bruce Kleinman, Vice President of Product Marketing at GLOBALFOUNDRIES. "What it means is that same set of design rules and models can be adopted, with no extra mask layer or special process required. This translates into cost saving and design flexibility without compromising on the power and optimization features."

Based on ARM's 1.0V/1.2V standard cells and memory compilers, GLOBALFOUNDRIES 55nm LPe 1V enables designers to optimize their design for speed, power and/or area and is especially beneficial for designers who are faced with power constraints in designing System-on-Chip solutions.

ARM offers a silicon-validated platform of 8-track, 9-track and 12-track libraries along with high-speed and high-density memory compilers for GLOBALFOUNDRIES' 55nm LPe process.

The 55nm LPe 1V is especially suited for high-volume, battery-operated mobile consumer devices, as well as a broad range of green or energy-saving products. PDK and EDA tools are available now, along with MPW shuttle availability.

Artisan memories offer flexible manufacturing options and are shipping in billions of products worldwide. Part of a broader platform of Artisan physical IP from 65nm to 20nm, these next-generation memories include low voltage and stand-by modes.


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