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     This story was printed from CdrInfo.com,

     located at http://www.cdrinfo.com.

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MIPI Alliance and the USB 3.0 Promoter Group today announced the completion of the SuperSpeed USB Inter-Chip (SSIC) specification.

The specification defines a chip-to-chip USB based internal interconnect for mobile devices as well as other platforms. SSIC offers MIPI Alliance's M-PHY high bandwidth and low power capabilities combined with SuperSpeed USB performance enhancements.

The M-PHYSM interface, a high speed serial interface, targets up to 2.9 Gbps per lane with scalability up to 5.8 Gbps per lane and offers a low pin count and power efficiency. SuperSpeed USB offers a 5 Gbps signaling rate, up to 10 times faster than Hi-Speed USB (USB 2.0), enhanced protocol and power management and backward compatibility with the existing USB device and software model.

"MIPI Alliance is focused on enabling enhanced performance within mobile devices," said Joel Huloux, MIPI Alliance Chairman of the Board. "With SSIC uniting the M-PHY physical layer with the SuperSpeed USB protocol layer, manufacturers and developers can benefit from the new mobile, low-power technology."

"SSIC opens the door for a broad range of USB-enabled functions to migrate into a huge mobile market," said Brad Saunders, USB 3.0 Promoter Group Chairman. "This chip-to-chip interface may also find its way back into the PC ecosystem for its low-power benefits."

The USB 3.0 Promoter Group developed the SSIC specification and has transitioned the specification?s management to the USB-IF. The USB 3.0 Promoter Group is now accepting adopters of the SSIC specification. To download both the SSIC specification and USB 3.0 adopter agreement, visit http://www.usb.org/developers/docs/.