Japanese maker of Dynamic Random Access Memory (DRAM) Elpida Memory today announced that it had finished development of a high-speed low-power 40nm 2-gigabit DDR3 SDRAM, the smallest in the DRAM industry.
The new 2-gigabit DDR3 SDRAM uses a smaller chip size to achieve a 44% higher chip yield per wafer compared with Elpida's 50nm DDR3 SDRAM and a 100% yield for DDR3 products that operate at 1.6Gbps, the highest speed standard for current DDR3. Compared with 50nm products, it uses about two-thirds less current and supports 1.2V/1.35V operation as well as DDR3 standard 1.5V, thus reducing power consumption by as much as 45%.
The development of the DRAM using a 40nm process focused on both performance and cost competitiveness. As a result, the investment cost of converting from 50nm manufacturing to 40nm manufacturing is expected to be almost zero. Moreover, a 65nm to 40nm process conversion can be accomplished with greater investment efficiency compared with a 65nm to 50nm conversion.
In addition to finer process technologies Elpida is also developing 65nm XS process technology that can compete with the 50nm process of other companies. Another development effort recently underway aims to produce smaller die size products based on the 65nm process.
Given this range of development choices, Elpida will have greater flexibility to deal with changing market conditions and in making decisions about the timing of investment in 40nm process equipment and the content of technology licensed to its Taiwan partners.
Elpida intends to increase 40nm process production to further reduce die costs. Meanwhile, the company continues to pursue higher productivity. The changeover as of July to a product-specific manufacturing system (separately managed manufacturing lines for mobile and PC-related products) at Elpida's Hiroshima Plant has already boosted yields. The combination of these cost savings and productivity improvements is expected to make Elpida more competitive. In addition, depending on future DRAM market conditions, Elpida believes it may be possible to increase the ratio of 40nm process line output to as much as 50% of total production.
Sample shipments of the 40nm 2-gigabit DDR3 SDRAM will start in November. Mass production is expected to begin before the end of 2009.