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Matsushita Electric Industrial today announced their development of the industry's most power-efficient MPEG-4 video decoder LSI, for use in various mobile phone systems such as W-CDMA, PDC and PHS. Samples will be shipped in May 2002; the new LSI will be formally announced at the International Solid-State Circuits Conference 2002, held in San Francisco, February 4-6, 2002.

Conventional MPEG-4 video decoder LSIs require minimum power of 50 mW, which quickly drains batteries and limits terminal continuous operating time. Matsushita's newly developed LSI, consuming only 11.1 mW, greatly extends operating time of MPEG-4 standard devices.

In video decoding with the new LSI, dedicated circuits (hardware engines) handle both routine and large-scale computation processes; the Digital Signal Processor (DSP) core handles non-routine processes. These improvements cut the operating frequency by half, to 27 MHz (partially 54 MHz), greatly improving power efficiency. Built-in 896Kbit SRAM with 0.18µm process and clock gating techniques also minimize power consumption. Since none of these features are process-dependent, the new LSI is easily integratable with other multimedia processing LSIs, significantly broadening the range mode mobile multimedia product applications.