Intel is developing an ultra-low power derivative of its high-performance 65 nanometer logic manufacturing process that will enable production of very low-power chips for mobile platforms and small-form factor devices.
The ultra-low power process will be Intel's second process based on 65nm process technology.
Intel's 65nm process provides both power consumption and performance benefits over Intel's current 90nm
manufacturing process. The new process provides Intel chip designers additional options in delivering the
circuit density, performance and power consumption required by users of battery-operated devices.
"People typically embrace mobile platforms that maximize battery life," said Mooly Eden, vice president and
general manager of the Intel Mobile Platforms Group. "Such products will be greatly enhanced by our new
ultra-low power manufacturing process. We will design future mobility platforms to take full advantage of both
leading-edge, 65nm manufacturing processes."
One of the factors in decreasing chip power consumption, which is important to mobile and battery-operated
devices, is improving the design of the transistor. Lost electricity leaking from these microscopic
transistors, even when they are in their "off" state, is a problem that is a challenge for the entire
industry.
"With the number of transistors on some chips exceeding one billion, it is clear that improvements made for
individual transistors can multiply into huge benefits for the entire device," said Mark Bohr, senior fellow
and director of Intel Process Architecture and Integration. "Test chips made on Intel's ultra-low power 65nm
process technology have shown transistor leakage reduction roughly 1000 times from our standard process. This
translates into significant power savings for people who will use devices based on this technology."
Intel's ultra-low power, 65nm process technology includes several key transistor modifications which enable
delivery of low power benefits while providing industry-leading performance. These transistor modifications
result in significant reductions in the three major sources of transistor leakage: sub-threshold leakage,
junction leakage and gate oxide leakage. The benefits of reduced transistor leakage are lower power and
increased battery life.