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     This story was printed from CdrInfo.com,

     located at http://www.cdrinfo.com.

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At the 2005 Symposium on VLSI Technology event, Toshiba Corp. and Sony Corp. announced an embedded DRAM process technology, which they have jointly developed at the 45 nm node.

The companies achieved the cell size of 0.069 μm2 by introducing the following three key techniques.

Firstly, Toshiba and Sony expanded the trench bottom area using technology called bottle etching, while introducing high-permittivity Al203 coating for capacitor insulation. Capacitor volume per unit area has been boosted 60% as a result, and the companies secured the capacitor volume equivalent to that of an obsolete model, while reducing the size of a capacitor.

Secondly, the companies employed a hybrid architecture combining spin on dielectric (SOD) and high-density plasma Si02 coating for trench isolation. This architecture eased STI response, reduced joint leakage and improved charge retention property. The technology also enabled to embed high aspect ratio STI devices more easily than before.

Lastly, Toshiba and Sony used Ultra Shallow Buried Strap technology, which forms Ni-salicide at joints (straps) between capacitors and transistors. This technology reduced the dimensions of a strap part and removed additional processing previously needed for conventional process technology.