Intel will try to further cut power consumption in its next generation of chips by using improved strained silicon, along with transistors that block power to other circuits, and other added features.
The Santa Clara, Calif.-based PC maker will incorporate a number of changes in its 65-nanometer manufacturing process, which will begin in 2005, said Mark Bohr, an Intel senior fellow and director of processor architecture and integration. Experimental SRAM chips have already been produced on the process.
Depending on the goals of the chip designer, circuits made on the 65-nanometer process can boost performance or cut power consumption or do both, but Intel is putting a definite accent on energy conservation. (65-nanometer refers to the average size of features of a chip. A nanometer is a billionth of a meter.)
The enhanced version of strained silicon--a technology that first appeared in Intel's 90-nanometer chips--can increase performance by 30 percent compared with nonstrained chips or provide a 4x improvement in inadvertent electricity leakage.
"With strained silicon, Intel is at least a generation ahead," Bohr said. "The enhanced strained silicon can be used to enhance drive current or reduce leakage."
Competitors IBM and Advanced Micro Devices have also begun to include strained silicon in chips.
Shrinking transistors and transistor components is at the heart of Moore's Law, which postulates that the number of transistors on a chip doubles every two years. Smaller transistors generally are faster (electrons have to cover less ground) and can result in smaller, cheaper, better and more energy-efficient chips. Ten million transistors in the test SRAM chips could fit on the tip of a ballpoint pen.
Following Moore's Law rigorously over the last 30 years, however, has resulted in extremely dense chips that are difficult to design, expensive to produce, tough to release on schedule and that exude as much heat, proportionally, as a rocket nozzle.
"As we scale dimensions, things get tougher," Bohr said.
Other alternations in the 65-nanometer generation will come in the oxide gate, a thin layer that helps control the flow of electrons between a transistor's source and the drain, a key element in controlling whether a computer sees a piece of data as a "1" or a "0."
In 65-nanometer chips, the length of gate oxide will get shorter, which will improve performance, but the gate oxide will retain its thickness. Typically, the oxide gets thinner in manufacturing transitions. By keeping the thickness the same, capacitance (a function of how much energy gets stored in a given material) goes down by 20 percent, which consequently reduces the potential for leakage.
Chips made on this process will also include sleep transistors that shut off power to other blocks of transistors.
Bohr couldn't quantify the power consumption these sleep transistors will curb, but potentially it could be quite a bit in both active power consumption and leakage.
"It is a noticeable gain in leakage reduction," he said.
The first chips made on the 65-nanometer process will come out in late 2005, Bohr said, first in Oregon and subsequently in Arizona and Ireland. He added that the transition from 90-nanometer to 65-nanometer probably won't be as taxing as the shift from 130-nanometer to 90-nanometer, which involved more changes in the underlying silicon.
Nonetheless, history shows that transitions in manufacturing take longer than expected. Designers often opt for performance over power savings.
"They are giving their circuit designers a lot of tools to control power, but it remains to be seen how they will use these skills," said Nathan Brookwood, an analyst with Insight 64.
Manufacturing transitions are also expected to start occurring at three-year, rather than two-year, intervals as time goes on. Many expect the 45-nanometer transition slated for 2007 to be particularly difficult, as chipmakers will likely have to change the materials in the transistor gate and gate oxide. By 2021 or so, the shrinking of transistor elements under Moore's Law is expected to come to an end.
Bohr added that Intel will adapt 248- and 193-nanometer lithography tools to produce 65-nanometer chips. Lithography tools "draw" transistors on wafers by shining light onto masks, maps of a chip's circuitry that cost millions of dollars to produce. The shadow cast by the masks (reduced greatly in size by lenses) in turn causes photoresistant chemicals on the wafer to react and expose metal.
New generations of lithography tools often take years to come to market and can cost $15 million or more, so adapting old tools for the new chips reduces risk exposure.
Intel will further engage in "dry" lithography for 65-nanometer manufacturing. Some manufacturers are currently exploring the possibility of immersion lithography, in which the wafers are submerged in water. The water helps focus the laser beam, which in turn lets engineers draw smaller circuits.
Extreme Ultraviolet, or EUV, lithography, which uses light with a much smaller wavelength, will start to replace 193-nanometer equipment toward the end of the decade.
One thing Intel's 65-nanometer chips won't contain is Silicon-on-Insulator, or SOI, an additional layer that advocates say cuts leakage power. In the early part of the decade, Intel experimented with adding what it called Ultra Thin SOI into its chips.
Now that notion has been scrapped, and Intel believes the power savings that Ultra Thin SOI would have brought will be accomplished through the tri-gate transistor, a future transistor that effectively triples the area inside a transistor for transporting electrons.