Monday, February 02, 2004
Sony '90-nm' chip may not be, analysis firm claims
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A key chip in Sony's PSX game console that the company says is built in a 90-nm process
technology was actually implemented in a 130-nm manufacturing process, according to the
Canadian technology and patent-analysis firm Semiconductor Insights. Sony vehemently denied
The allegation goes to the heart of Sony's credibility as a technology leader as the
Japanese consumer electronics giant puts renewed emphasis on its semiconductor business.
Last May, Sony said they had integrated two complex ICs, the Emotion Engine processor and
Graphics Synthesizer graphics chip, into a single 90-nm device with 53.5 million transistors
and 4 Mbytes of embedded DRAM. The chip's name — EE+GS@90nm — reflected both its integration
level and production process. Sony said the chip was ready for volume production at that
In November, Sony launched the DESR-5000 and DESR-7000 models of its PSX game console and
DVD recorder and said they were based on the EE+GS@90nm. Semiconductor Insights said it
removed the chip from a DESR-5000 model bought in Japan and found it was implemented using
130-nm process technology, with a die size of 90 mm2. That contradicts Sony's claim about
the process, which has an 86-mm2 die size, the Canadian analyst added.
“We took a cross-section through a dense logic area and measured the smallest gate lengths
we could find and compared them with the ITRS road map,” said Edward Keyes, chief technology
officer of Semiconductor Insights, referring to the International Technology Roadmap for
Semiconductors. “That says an LG [gate length] of 37 nm equates to a 90-nm process. We found
the smallest LG was 70 nm, which equates to a 130-nm process. The ITRS specifies an LG of 65
nm for a 130-nm process.”
Further, said Keyes, “We also looked at the metal-1 pitch and that too measured much closer
to a 130-nm process than to a 90-nm process. We also looked at the embedded-DRAM pitch.”
Keyes said the company took a number of slices through the chip to make sure the
measurements were representative. “It's clear that it's a 130-nm chip, not a 90-nm chip, as
defined by the ITRS,” said Keyes.
Sony quickly rejected that assessment and reiterated its contention that the EE+GS device is
“fabricated in a 90-nm process as defined by the ITRS road map,” a Sony spokesman said. The
single-chip EE+GS processor has never been made in a 130-nm process, not even in an
engineering sample, the spokesman added.
Before merging the EE and GS processors into one, Sony fabricated the Graphics Synthesizer
chip using a 130-nm process. The Emotion Engine was produced in a 150-nm process, he added.
Referring to “misunderstandings” in the way Semiconductor Insights measured the EE+GS
processor, engineering sources at Sony acknowledged that Sony used a geometry rule “a little
bit more relaxed than 90 nm” in certain portions of the EE part of the design. Sony said the
GS block was completely redesigned based on a 90-nm library. The embedded-DRAM block is one
generation behind the logic, and uses a 130-nm process, according to a second Sony
The combined chip is produced in CMOS4, a 90-nm process jointly developed by Sony, Sony
Computer Entertainment and Toshiba Corp. Toshiba began shipments of the first silicon
fabricated on that process in November 2002. Then Sony started volume production of the PSX
chip using the process at Oita TS Semiconductor, its joint venture with Toshiba. Sony
Computer Entertainment's Fab 2 in Nagasaki, Japan, is also running the CMOS4 process, Sony
Toshiba said it followed criteria used widely for logic when it defined the CMOS4 process.
There may be some difference in the viewpoints of Toshiba and Semiconductor Insights, a
Toshiba spokesman said.
Toshiba uses the metal pitch, not gate length, to define the 90-nm process, the spokesman
said. For the 90-nm process, the L and S of metal-1 measure 240 nm, or 120 nm for each line
and space, which corresponds to the 90-nm node, according to a source close to the process
technology. The same source pointed out that transistor gate length varies even in the same
process node. If high performance is required, the gate length is made shorter, but the
geometry can be lax when less performance is required.
Sony insisted that the EE+GS processor is a 90-nm device, and said it never fed the public
false information about the chip or its production.
“There is no 'definition' of measurement and semiconductor manufacturers tend to use
favorable figures,” said Satoru Rick Oyama, senior analyst at Lehman Brothers Japan Inc. “It
is not important whether it is on a 90-nm process or not. What is important is to lower the
cost by integrating two chips into one. And Sony did that.”
Semiconductor Insights' allegation, however, sounded credible to those familiar with the
chip industry's struggle to improve 90-nm yield rates. “Nobody is pushing [90-nm logic] to
real volume production yet,” said Joe D'Elia, director of iSuppli Europe, a market research
firm. “The closest to it is probably Intel Corp.”
To meet the demand for chips in PSX consoles, D'Elia said that both Toshiba and Sony must
have already had adequate engineering lines pumping out quite a few thousand logic chips in
the 90-nm process by the middle of 2003. “That just doesn't tie up with what we see in the
semiconductor industry in general,” he said.
Sony declined to comment on the production capacity and yield rate of the CMOS4 process at
its Nagasaki plant. The company has said it sees an urgent need to strengthen its core
consumer products by leveraging its IC technology. Katsuaki Tsurushima, electronics chief
technology officer at Sony Corp., told EE Times last fall that Sony's future as a leader in
the consumer industry rests upon “our own key device technologies, including
Keyes said he wasn't sure where the chip Semiconductor Insights analyzed had been made. The
names of both Toshiba and Sony are inscribed on the die, he said. Keyes said a 130-nm
transition for the EE+GS chip made sense, since the separate Emotion Engine and Graphics
Synthesizer used in the Playstation had been fabricated using a mix of 0.25-micron and
0.18-micron process technologies.