Tuesday, February 18, 2014
Intel Releases Xeon Processor E7 v2 Family For Big Data
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To help companies in a variety of industries turn data into actionable insights, Intel today introduced the Intel Xeon processor E7 v2 family.
Using analytics enables businesses to make decisions that
improve top-line and bottom-line results. The Intel Xeon
processor E7 v2 family, code-named Ivytown, delivers new capabilities to process
and analyze large amounts of data to unlock information.
"The advanced performance, memory capacity and reliability of the Intel Xeon processor E7 v2 family enable IT organizations to deliver real-time analysis of large data sets to spot and capitalize on trends, create new services and deliver business efficiency," said Diane Bryant, senior vice president and general manager of Intel's Data Center Group.
The Intel Xeon processor E7 v2 family is a 2, 4 or 8-socket
platform based on Intel Core microarchitecture (formerly
codenamed Ivy Bridge) and manufactured on 22-nanometer process
technology. With configurations supporting up to 15 processing
cores and up to 1.5 terabytes (TB) of memory per socket, the
new processor family achieves twice the average performance of
the previous generation.
It has also triple the memory capacity of the previous
generation processor family, allowing much faster data
analysis. In-memory analytics places and analyzes an entire
data set - such as an organization's entire customer database
- in the system memory rather than on traditional disk drives.
To reduce data bottlenecks, the Intel Xeon Processor E7 v2
family features Intel Integrated I/O, Intel Data Direct I/O
and support for PCIe 3.0, achieving up to four times the I/O
bandwidth over the previous generation and providing extra
capacity for storage and networking connections.
The Xeon E7 v2 chips will run at clock speeds between 1.4GHz and 3.8GHz, and draw between 40 watts and 150 watts of power. The chip also has 37.5MB in cache.
The new processor family continues Intel's tradition of
delivering reliability, availability and serviceability (RAS).
Intel Run Sure Technology is designed for "five nines"
solutions essential for business-critical data by reducing the
frequency and cost of planned and unplanned downtime.
New RAS features implemented in hardware and firmware include:
- PCIe Live Error Recovery (LER): This feature allows the
system to bring down the PCIe link associated with the PCIe
root port where an uncorrected (fatal or non-fatal) fault is
detected in either an incoming or outgoing transaction without
resetting the entire system. It also allows Firmware/Software
assisted link retraining and recovery. LER also protects
against the transfer of potentially corrupt data to the disk.
- Enhanced Machine Check Architecture Gen 1 (eMCA1): This
feature enhances the existing Machine Check Architecture (MCA)
by implementing Firmware First Model (FFM) of the error
reporting (logging and signaling). FFM is a server RAS
paradigm where all the error events are first signaled to
platform specific firmware. The firmware processes the error
logs and decides if and when to notify the Operating System or
Application software layers of an error. EMCA14 can be
configured to provide enhanced error log information to the OS
and VMM that can be used to implement advanced diagnostic and
predictive failure analysis7 (PFA) for the system. Legacy MCA
provides physical address of the memory location when a
corrected fault occurs, but it is challenging for PFA software
to map it to an actual physical DIMM. EMCA1 allows providing
such additional error logs to the PFA software.
- Machine Check Architecture (MCA) recovery for I/O: The MCA
recovery for I/O allows uncorrected, both fatal and non-fatal,
I/O errors to be reported through the MCA mechanism. Intel
Xeon Processor E7 families incorporate PCI Express Advanced
Error Reporting (AER) architecture to report (log and signal)
uncorrected and corrected I/O errors. Normally uncorrected I/O
errors are signaled to the system software either as AER
Message Signaled Interrupt (MSI) or via platform specific
mechanisms such as System Management Interrupt (SMI) and/or
physical Error Pins. The signaling mechanism is controlled by
BIOS and/or platform firmware. As a part of this new feature
the processor has added a new Machine Check bank called IOMCA
and allows logging and signaling of IO uncorrected errors
through standard Machine Check Architecture. It logs the Bus,
Device, and Function information associated with the PCI
Express port, thus allowing error handling software to
identify the source of error faster. By using this feature to
signal the uncorrected I/O errors through the MCA mechanism,
the errors can be communicated to the software layer (OS, VMM
and DBMS) to improve error identification and recovery.
- Machine Check Architecture (MCA) recovery - Execution Path:
The MCA recovery - Execution Path feature offers the
capability for a system to continue to operate even when the
processor is unable to correct data errors within the memory
sub-system and allows software layers (OS, VMM, DBMS, and
Applications) to participate in system recovery. This feature
can handle hardware uncorrected errors occurring within the
memory sub-system including main memory, last level caches,
and mid-level caches. When the processor detects a fault
within the memory sub-system, it will attempt to correct the
fault. In most of the cases, memory faults are corrected by
the processor. However, if the error cannot be corrected, the
processor will notify the operating system (OS) using Machine
Check Exception6 (MCE) and logs the error as an uncorrected
recoverable error (UCR). The OS analyzes the log and verifies
that the recovery is possible. If the recovery is possible
then the OS un-maps the affected page(s) and triggers a SIGBUS
event to the application. If the error is detected in an
instruction code then the instruction fetch unit (IFU) is
notified and MCE is triggered by the IFU. In this case, the OS
will reload the affected page containing the instruction to a
new physical page and resume normal execution. If the error
is detected within the data space then the Data Cache Unit
(DCU) is notified and the MCE is triggered by the DCU. In this
case, the OS will notify the application through the SIGBUS
event, and it is up to the application to take further action.
The affected application is then responsible for reloading
the data. If the data was already modified and the
application cannot reload the data from the disk, the affected
application will be terminated (i.e. a system reset will not
be required, and other applications will continue to operate
normally). In order to take full benefit of the MCA recovery
- Execution Path feature, applications are required to be
Starting today, system manufacturers from around the world
will announce more than 40 Intel Xeon processor E7 v2
Dell announced the new PowerEdge R920 server, which is twice as fast in responding to Oracle queries, said Brian Payne, executive director of server solutions.
The four-socket R920 will support up to 6TB of memory. It is compatible with the NVMe (Non-Volatile Memory Express) storage interface, an emerging protocol for solid-state drives. NVMe is expected to replace protocols such as SATA.
Hewlett-Packard announced the Proliant DL580 Gen8 server, which is also a four-socket server with support for up to 6TB of memory. HP claimed a 2.3 times improvement in server performance compared to predecessors, and twice the SSD performance with the company's Smart Array SAS controllers. HP is also claiming 2.7 times better I/O performance with support for PCI-Express 3.0.