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Monday, June 3, 2013
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ARM AMBA 5 CHI Specification To High Performance, Highly
SoC Technology
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ARM today announced, at DAC 2013, the AMBA 5 CHI
(Coherent Hub Interface) specification which will enable
ARM Cortex-A50 series processors to work together in
high-performance, coherent processing "hubs", and to
deliver the high data rates in servers and networking.
The AMBA 5 CHI specification has been developed by ARM
with the participation of industry players including ARM
semiconductor partners, third party IP providers and the
EDA industry. The AMBA 5 CHI protocol is used by the
ARMv8 architecture-based Cortex-A57 and Cortex-A53
processors and the CoreLink DMC-520 Dynamic Memory
Controller. It is also used by the CoreLink CCN-504
Cache Coherent Network, which is capable of 1 Terabit/s
data flows.
AMBA 5 CHI has been developed to support high frequency,
non-blocking data transfers between multiple fully
coherent processors. The interface supports distributed
level 3 caches, very high rates of I/O coherent
communication, and Quality of Service (QoS)
functionality. The AMBA 5 CHI architecture also
introduces a layered model to allow implementations to
separate communication and transport protocols, which
enables the optimal trade-off between performance, power
and area.
"To ensure that our silicon partners can rapidly deploy
IP and SoCs implementing the AMBA 5 CHI protocol, ARM
has worked closely with many partners across the SoC
design ecosystem," says Noel Hurley, vice president,
Marketing and Strategy, Processor Division, ARM.
"Through early engagement we have enabled our EDA
partners to develop a wide range of verification IP, and
debugging and performance analysis tools to accelerate
the implementation of AMBA 5 CHI based SoCs."
The AMBA 5 CHI specification and associated protocol
checkers (SystemVerilog assertions) are available, at no
cost, under license to companies integrating or
developing IP that implements the AMBA 5 CHI protocol. |
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