Thursday, December 18, 2014
Search
  
Tuesday, October 09, 2012
 TSMC Says 20nm and CoWoS Design Infrastructure Ready
You are sending an email that contains the article
and a private message for your recipient(s).
Your Name:
Your e-mail: * Required!
Recipient (e-mail): *
Subject: *
Introductory Message:
HTML/Text
(Photo: Yes/No)
(At the moment, only Text is allowed...)
 
Message Text: TSMC has delivered two foundry-first reference flows supporting 20nm and CoWoS (Chip on Wafer on Substrate) technologies, within the Open Innovation Platform (OIP).

TSMC's 20nm Reference Flow enables double patterning technology (DPT) design using proven design flows. EDA vendors' tools are qualified to work with TSMC 20nm process technology by incorporating DPT aware place and route, timing, physical verification and design for manufacturing (DFM). TSMC claims that the new silicon-validated CoWoS Reference Flow enables multi-die integration to support high bandwidth and low power, can achieve fast time?to- market for 3D IC designs.

"These Reference Flows give designers access to TSMC's advanced 20nm and CoWoS technologies," said TSMC Vice President of R&D, Dr. Cliff Hou. "Delivering advanced silicon and manufacturing technologies as early and completely as possible to our customers is a chief goal for TSMC and its OIP design ecosystem partners."

TSMC's 20nm Reference Flow enables 20nm design with DPT aware capabilities to reduce design complexity and deliver required accuracy. DPT enablement includes pre-coloring capability, new RC extraction methodology, DPT sign-off, physical verification and DFM. In addition, TSMC and its ecosystem partners design 20nm IP for DPT compliance to accelerate 20nm process adoption.

The CoWoS Reference Flow enables 3D IC multi-die integration. The new CoWoS Reference Flow allows a smooth transition to 3D IC with minimal changes in existing methodologies. It includes the management of placement and routing of bumps, pads, interconnections, and C4 bumps; combo-bump structure; accurate extraction and signal integrity analysis of high-speed interconnects between dies; thermal analysis from chip to package to system; and an integrated 3D testing methodology for die-level and stacking-level tests.

The Custom Design Reference Flow enables DPT in 20nm custom layouts. It provides solutions to 20nm process requirements, including a direct link with simulators for the verification of voltage-dependent DRC rules, and integrated LDE solutions and handling of HKMG technology. RF Reference Design Kit provides new high frequency design guidelines. These consist of 60GHz RF model support, high performance Electromagnetic (EM) characterization that enables customer design capability through the examples of 60GHz front-to-back implementation flow and Integrated Passive Device (IPD) support.

In related news, TSMC announced unconsolidated net sales of NT$42.82 billion (US$1.46 billion) for September, a decrease of 12.4% on month and an increase of 30.3% on year.

Unconsolidated revenues for January through September 2012 totaled NT$370.39 billion.

Consolidated revenues for the first nine months of 2012 totaled NT$374.94 billion, an increase of 16.3% from a year ago. Consolidated third quarter revenues came to a total of NT$141.38 billion, reaching a record high for TSMC.

However, TSMC is expected to see its revenues drop in a range of 10% in the fourth quarter due to seasonality, as well as the absence of strong global demand for PCs and notebooks.
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2014 - All rights reserved -
Privacy policy - Contact Us .