Tuesday, July 29, 2014
Search
  
Wednesday, November 16, 2011
 Intel Reveals 1 TFLOP/s Knights Corner, Next-generation Xeon E5 Chips
You are sending an email that contains the article
and a private message for your recipient(s).
Your Name:
Your e-mail: * Required!
Recipient (e-mail): *
Subject: *
Introductory Message:
HTML/Text
(Photo: Yes/No)
(At the moment, only Text is allowed...)
 
Message Text: At SC11, Intel revealed details about the company's next-generation Intel Xeon processor-based and Intel Many Integrated Core (Intel MIC)-based platforms designed for high-performance computing (HPC). The company also outlined new investments in research and development that will lead the industry to Exascale performance by 2018.

During his briefing at the conference, Rajeeb Hazra, general manager of Technical Computing, Intel Datacenter and Connected Systems Group, said that the Intel Xeon processor E5 family is the world's first server processor to support full integration of the PCI Express 3.0 specification. PCIe 3.0 is estimated to double the interconnect bandwidth over the PCIe 2.0 specification while enabling lower power and higher density server implementations. New fabric controllers taking advantage of the PCI Express 3.0 specification will allow more efficient scaling of performance and data transfer with the growing number of nodes in HPC supercomputers.

The early-performance benchmarks revealed that the Intel Xeon E5 delivers up to 2.1 times more performance in raw FLOPS (Floating Point Operations Per Second as measured by Linpack) and up to 70 percent more performance using real-HPC workloads compared to the previous generation of Intel Xeon 5600 series processors.



Two months since its initial shipments to supercomputer centers, Intel Xeon E5 processors now power 10 systems on the TOP500 list.

As previously announced, the upcoming Intel Xeon processor E5 family will power several other future supercomputers, including the 10 PFLOPS "Stampede" at Texas Advanced Computing Center, the 1.6 PFLOPs "Yellowstone" at The National Center for Atmospheric Research, the 1.6 PFLOPS "Curie" at GENCI, the 1.3 PFLOPS system at International Fusion Energy Research Center (IFERC) and more than 1 PFLOPS "Pleiades" expansion at NASA.

Intel started shipping the Intel Xeon processor E5 family to a small number of cloud and HPC customers in September, with broad availability planned in the first half of 2012.

During SC'11 Intel also provided details on its expanded lineup of server boards and chassis, including products specifically optimized for HPC, which will be ready to support the launch of the Intel Xeon Processor E5.

Intel also reiterated its commitment to delivering the platform for highly parallel applications.

The first presentation of the first silicon of "Knights Corner" co-processor showed that Intel architecture is capable of delivering more than 1 TFLOPs of double precision floating point performance (as measured by the Double-precision, General Matrix-Matrix multiplication benchmark -- DGEMM). This was the first demonstration of a single processing chip capable of achieving such a performance level.

The 22nm "Knight's Corner" co-processor compute accelerator is boasting over 50 cores outstripping Nvidia?s Tesla 2090 accelerator.

Showing off the very first silicon available, Intel?s Rajeeb Hazra, general manager of technical computing at the Intel datacenter and connected systems group said the single 1TFLOP/s chip was the equivalent of the entire AsciiRed system built back in 1997, consisting of 9298 Pentium II Xeon processors.That system made up 72 cabinets of computing power.

"Intel first demonstrated a Teraflop supercomputer utilizing 9,680 Intel Pentium Pro Processors in 1997 as part of Sandia Lab's "ASCI RED" system," Hazra said. "Having this performance now in a single chip based on Intel MIC architecture is a milestone that will once again be etched into HPC history."

"Knights Corner," the first commercial Intel MIC architecture product, will be manufactured using Intel's latest 3-D Tri-Gate 22nm transistor process and will feature more than 50 cores. When available, Intel MIC products will offer both high performance from an architecture specifically designed to process highly parallel workloads, and compatibility with existing x86 programming model and tools.

Hazra said that the "Knights Corner" co-processor is very unique as, unlike traditional accelerators, it is fully accessible and programmable like fully functional HPC compute node, visible to applications as though it was a computer that runs its own Linux-based operating system independent of the host OS.



One of the benefits of Intel MIC architecture is the ability to run existing applications without the need to port the code to a new programming environment. This will allow scientists to use both CPU and co-processor performance simultaneously with existing x86 based applications, saving time, cost and resources that would otherwise be needed to rewrite them to alternative proprietary languages.

Investment in Exascale Computing Labs

As previously announced at the International Supercomputing Conference 2011 in Hamburg, Germany, Intel's goal is to deliver Exascale-level performance by 2018 (which is more than 100 times faster performance than is currently available) while only requiring two times the power usage of the current top supercomputer. Fundamental to achieving that goal is working closely with the HPC community, and today Hazra announced several new initiatives that will help to achieve that goal.

Intel and the Barcelona Supercomputing Center (BSC) have signed a multi-year agreement to create the Exascale Laboratory in Barcelona, Intel's fourth European Exascale R&D lab that joins existing sites in Paris, Juelich (Germany) and Lueven (Belgium). This new laboratory will focus on scalability issues in the programming and runtime systems of Exascale supercomputers.

Additionally, the Science and Technology Facilities Council (STFC) and Intel have signed a memorandum of understanding to develop and test technology that will be required to power the supercomputers of tomorrow. Under this initial agreement, STFC?s computational scientists at its Daresbury Laboratory in England and Intel will work together to test and evaluate Intel's current and future hardware with leading software applications to ensure that scientists are ready to exploit Intel's supercomputer systems of the future.

Intel Capital, Intel's global investment and M&A organization, also unveiled a $100 million Intel Capital AppUpSM Fund. The fund will invest in software tools and services companies developing innovative applications and digital content for the mobile and PC ecosystem available at the Intel AppUpSM center, Intel's app store for netbooks, consumer laptops and Ultrabooks.

The initial two investments include Urban Airship, a mobile platform-as-a-service company and 4tiitoo, a German OSV and tablet device developer. The announcement was made at the 12th annual Intel Capital Global Summit.

The Intel Capital AppUp Fund will invest in companies producing infrastructure, middleware applications and digital content across the continuum of connected devices in application developer-centric equity deals all over the world. The fund is built to advance computing innovations based on Intel architecture in key areas such as digital media consumption, context-aware computing and infrastructure applications. While the investments will focus across multiple technologies and devices, key areas include cross-platform technologies such as HTML5, as well as experiences designed specifically for Ultrabooks.
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2014 - All rights reserved -
Privacy policy - Contact Us .