Thursday, May 26, 2011
TSMC Completes 28nm Design Infrastructure
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TSMC announced today that 28nm support within the Open Innovation Platform (OIP) design infrastructure is fully delivered, as demonstrated by 89 new 28nm designs scheduled to tapeout.
The company will also introduce OIP enhancements, including the delivery
of Reference Flow 12.0 and Analog/Mixed Signal (AMS) Reference Flow 2.0 at
the upcoming Design Automation Conference (DAC) in San Diego California.
OIP is a program that involves more collaboration between the foundery and
its clients at the early stages of the design phase.
TSMC?s 28nm design ecosystem is ready today with foundation collateral
such as DRC, LVS and PDKs; foundation IP, including standard cell
libraries, standard I/O, efuse and memory compilers; and standard
interface IP such as USB, PCI and DDR/LPDDR. The company's customers can
download these materials at TSMC Online.
"Collaboration with the Electronic design automation (EDA) community for
28nm has been equally thorough in order to achieve tool consistency for
improved design results. One example is a unified DFM engine for 28nm now
in use by Cadence, Synopsys and Mentor," the company said.
Reference Flow 12.0 features various enhancements in: two-and-a-half
dimensional and three dimensional integrated circuits (2.5-D/3-D ICs)
using silicon interposer and through silicon via (TSV) technologies; 28nm
model-based simulation DFM speed-up; and advanced Electronic System Level
(ESL) design initiative enabling TSMC?s process technology PPA (power,
performance, and area) to be integrated into system level design. In
addition, Reference Flow 12.0 will disclose TSMC's 20nm Transparent Double
Patterning design solution for the first time as part of the on-going
build up of 20nm design capability within OIP.
AMS Reference Flow 2.0 offers a multi-partner AMS design flow addressing
the complexity of 28nm process effects and design challenges for superior
DFM and RDR compliance and reliability.
"TSMC customers can immediately take advantage of our 28nm advanced
technology and manufacturing capacity while preparing for 20nm in the near
future," said Cliff Hou, TSMC Senior Director, Design and Technology
Platform. "We have enabled customers to achieve their product design goals
by closely collaborating with our EDA and IP partners to deliver a solid
28nm design ecosystem. In addition, the introduction of Reference Flow
12.0 and AMS Reference Flow 2.0 address critical design issues for the
next generation of 28nm and 20nm applications."
New At DAC
Reference Flow 12.0 and Transparent Double Patterning for 20nm
20nm is the first process node where metal pitch is beyond the
lithographic capabilities of existing exposure systems. Double patterning
is the key enabling lithographic technology to overcome the litho
resolution limitations without resorting to as yet production unproven
technologies as EUV. TSMC?s Transparent Double Patterning solution enables
system and chip designers to access 20nm technology, implemented with
double patterning, without any modifications to their current design
methodologies or flows. This technology is being delivered to EDA partners
and certified for delivery in their commercial products.
2.5D Silicon Interposer
Typically a 2.5D design includes multiple dies to be integrated with a
silicon interposer, which is implemented in different technology. TSMC
said that "Reference Flow 12.0 features new design capabilities in
floorplaning, P&R, and IR-drop and thermal analysis to accommodate
multiple nodes simultaneously, as well as a new design for test
methodology for 2.5D design."
28nm Power, Performance and DFM Design Enablement
Timing degradation from wire and via resistance becomes more significant
in finer geometry technologies: "Reference Flow 12.0 introduces an
enhanced routing methodology to minimize via counts, change layers for
routing, or widen wires to mitigate the impact of wire and via
resistance," the cmpany said.
Leakage current increases as threshold voltage and gate oxide thickness
decrease in 28nm. Multi-Mode Multi-Corner (MMMC) leakage optimization
accommodates different Vt options and gate-biased libraries enabling
designers to more effectively reduce leakage.
Finally, in order to minimize the design cycle time of hotspot checking
and fixing in 28nm, a new "hotspot filtering engine" is added to the DFM
Data Kit (DDK) to speed up model-based DFM analysis.
AMS Reference Flow 2.0
AMS2.0 helps designers to ensure the compliance of DFM and Restricted
Design Rules (RDR) for custom design in 28nm. It demonstrates correct
design configurations and options setting to use TSMC PDKs and DFM
utilities. In addition, TSMC applies accumulated reliability lessons
learned, and collaborates with its partners to introduce new approaches
to filter out known potential reliability defects. TSMC and 21 OIP
ecosystem partners will present and showcase the features and benefits of
Reference Flow 12.0 and AMS Reference Flow 2.0.
RF Reference Design Kit 3.0
For RF designers, TSMC will introduce a new RF Reference Design Kit (RF
RDK 3.0) which includes a silicon correlated, 60GHz Millimeter Wave design
kit, and an innovative way for its customers to design with their own
choice of inductors through EM (eletromagnetic) simulation.