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Wednesday, January 26, 2011
 Intel and IBM To Discuss Server Processors at ISSCC
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Message Text: At the International Solid State Circuit Conference (ISSCC), which will be held in San Francisco from Feb. 20-24, Intel will discuss its next-generation Itanium chip code-named Poulson and IBM will present its its zEnterprise 196 quad-core server chip.

IBM's Enterprise 196 quad-core server chip is clocked at 5.2GHz and it already powering IBM's zEnterprise mainframe systems. The chip uses 1.4 billion transistors and includes a high-speed 24MB shared DRAM L3 cache. IBM will describe the challenges met in order to meet this high-frequency design objective, including significant timing, power and noise problems which had to be resolved.

Intel's Itanium chips are designed for high-end servers that require high uptime and reliability. The Poulson chips, which will succeed the existing Itanium processors code-named Tukwila, implemented in 32nm CMOS with 9 layers of Cu contains a record 3.1 billion transistors, an improvement from the 65nm process used to make Tukwila chips. The die measures 18.2?29.9mm2. The processor has 8 multi-threaded cores, a ring-based system interface and combined cache on the die is 50MB. High speed links allow for peak processor-toprocessor bandwidth of up to 128GB/s and memory bandwidth of up to 45GB/s, according to Intel.

Intel will also duscuss a 32nm westmere-eX Xeon enterprise processor, a monolithic 10-core Xeon Processor designed in a 32nm 9M process with a shared L3 cache. Intel has introduced low power modes to cut idle power compared to the previous generation processor. A 2nd order CTLE and temperature compensation are implemented in the I/O receiver to enable link survivability even with low RX margins. Core- and cache-recovery techniques have also maximize yield, according to Intel.

Staying with Intel, the company will also described the recently released 32nm Sandy Bridge processor that integrates up to 4 Intel Architecture (IA) cores, a power/performance optimized graphic processing unit (GPU) and memory and PCIe controllers in the same die. Intel will talk about some of the integration methods, power saving techniques and the clock distribution network.

AMD will also have a presence at the conference. The company will design Solutions for the Bulldozer 32nm Soi 2-core processor, which contains 213M transistors in an 11-metal layer 32nm high-k metalgate SOI CMOS process and is designed to operate from 0.8 to 1.3V. AMD claims that this micro-architecture improves performance and frequency while reducing area and power over a previous AMD x86-64 CPU in the same process. The design reduces the number of gates/cycle relative to prior designs, achieving 3.5GHz+ operation in an area (including 2MB L2 cache) of 30.9mm2.

Staying with AMD, the company will talk about its low-power Zacate SoC based on its Fusion technology. Zacate combines x86 CPU and Radeon GPU on a single 40nm bulk CMOS die. The SoC uses an internal bus architecture and design techniques to optimize performance and memory bandwidth without compromising on power savings. Fine-grain power gating, dynamic voltage/frequency scaling and enhanced display refresh are key enablers for low-power operation.

Another player aiming to gain a foothold in the high-end chip market is the Chinese government's Chinese Academy of Sciences, which will be presenting its next-generation Godson processor. The Godson-3B processor is an 8-core high-performance processor implemented in a 65nm CMOS LP/GP mixed process with 7 layers of Cu metallization. It contains 582.6M transistors in a 299.8mm2 area. The highest frequency of Godson-3B is 1.05GHz. Its peak performance is 128/256GFLOPS for double/single-precision with 40W power consumption.
 
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