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Tuesday, December 07, 2010
 25nm NAND And 20nm Manufacturing Technology Platform on Stage Of IEDM 2010
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Message Text: Intel-Micron will talk about its 25nm 64Gb MLC NAND technology and TSMC's will present a 20nm technology platform at the IEEE International Electron Devices Meeting (IEDM) forum held in San Francisco December 6 - 8, 2010.

Researchers from Intel and Micron Technology will describe the technology they have developed to produce the world?s first 25nm 64Gb multi-level cell (MLC) NAND memory, with an incredibly small cell size of 0.0028μm2. The half-pitch of the cell is 24.5nm in the word line direction and 28.5nm in the bit line direction. An unwanted consequence of this aggressive word-line pitch scaling is increased word line-to-word line capacitance, as well as increased cell-to-cell interference. An air gap was introduced between word lines to overcome both these problems.

The researchers also optimized the insulating tunnel oxide and inter-poly dielectric of the cell, as well as the surrounding dielectric, to minimize leakage and trapping, resulting in performance similar to previous generations.

Taiwan-based TSMC will also unveil a complete high-performance 22/20nm CMOS logic technology at IEDM 2010. It features FinFET transistor architectures, aggressive 193nm immersion lithography, SiGe stressors, metal gates and high-k dielectrics. The FinFETs, built with dual-epitaxy and multiple stressors, demonstrate outstanding performance in both n- and p-channel versions, enabling maximum design flexibility, according to TSMC's researchers. N-/P-channel on-current is 1200/1100μA/μm respectively, while off-current for both N and P versions is 100nA/μm. The researchers used the new technology to build a dense 0.1μm2 SRAM memory cell, which had excellent noise characteristics (90mV noise margin) even at a low 0.45V operating voltage.
 
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