TSMC New Standard Cell Slim Library Reduces Logic Area

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Tuesday, June 15, 2010

TSMC New Standard Cell Slim Library Reduces Logic Area

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Taiwan Semiconductor Manufacturing Company today introduced the first Slim Library that reduces system-on-chip (SoC) routed logic block area by 15 percent compared to blocks routed through current standard cell libraries.

The library targets TSMC's 65nm LP process technology and fits existing implementation flows for easy adoption. Designers can use the new Slim Library in existing or new designs without change to design tools and implementation methodologies.

Slim Library is the result of the AreaTrim design and process co-optimization program between the TSMC and Tela Innovations. The library is based on Tela's patented layout style and TSMC's process optimization. The two companies demonstrated the 15% area improvement through synthesis and timing-driven place and route implementations on multiple versions of widely used microprocessor cores.

The new library's layout style draws a lithography-optimized pattern with uniform density through unidirectional poly on a fixed pitch and improved manufacturing process control to reduce area. As a result, Slim Library achieves gate densities of up to 1 million gates per square millimeter.

Slim Library is re-designed into 8 tracks from the traditional 9-track configuration, yet provides equivalent performance and power. The library includes Multiple Vt options and power management cells along with full set of characterization corners.

The new 65LP Slim Library is available now in limited release through the TSMC Online customer design portal (http://online.tsmc.com/online) or by contacting local TSMC account management or support representatives. General release is targeted for the first quarter of 2011.