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Saturday, January 30, 2010
 Intel and Micron to Ship First 25nm Flash Memory Chips
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Message Text: Intel and Micron wil start shipping the industry's first 25-nanometer flash memory chips in Q2 of 2010.

The IM Flash Technologies, the joint venture between Intel and Micron, plan to release the new 64 gigabit (8 gigabyte) MLC (multi-level cell) NAND flash memory chip.

The new chips are aimed at solid-state drives , smartphones, and portable media players.

NAND flash memory stores data and other media contained in consumer electronics products, retaining information even when the power is turned off. The drive toward smaller NAND processes enables the continued development and introduction of new uses for the technology. Not only is the 25nm process the smallest NAND technology, it is also the smallest semiconductor technology in the world - a technological accomplishment that continues the advancement of more music, video, and other data in today?s consumer electronics and computing applications.

Manufactured by IM Flash Technologies (IMFT), Intel and Micron's NAND flash joint venture, the 25nm process produces 8 gigabytes (GB) of storage in a single NAND device, creating a high-capacity storage solution for today's tiny consumer gadgets. It measures just 167mm2-- small enough to fit through the hole in the middle of a compact disc (CD), yet packs more than 10 times the data capacity of that CD (a standard CD holds 700 megabytes of data).

"To lead the entire semiconductor industry with the most advanced process technology is a phenomenal feat for Intel and Micron, and we look forward to further pushing the scaling limits," said Brian Shirley, vice president of Micron?s memory group. "This production technology will enable significant benefits to our customers through higher density media solutions."

The 25nm, 8GB device is sampling now and is expected to enter mass production in the second quarter of 2010. For consumer electronics manufacturers, the device provides the highest-density in a single 2 bits-per-cell multi-level cell (MLC) die that will fit an industry-standard, thin small-outline package (TSOP). Multiple 8GB devices can be stacked in a package to increase storage capacity. The new 25nm 8GB device reduces chip count by 50 percent compared to previous process generations, allowing for smaller, yet higher density designs and greater cost efficiencies. For example, a 256GB solid-state drive (SSD) can now be enabled with just 32 of these devices (versus 64 previously), a 32GB smartphone needs just four, and a 16GB flash card requires only two.

 
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