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 AMD Technology Update
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Message Text: Earlier on Wednesday, AMD presented updates on its business, financials and technology, at the company's annual Financial Analyst Day at the New York Stock Exchange.

The event was hosted by members of the AMD executive team, and featured presentations and news disclosures that provided updates on AMD business, financials and technology.

AMD Chairman and CEO Hector Ruiz said during his presentation that customer demand is strong and the company expects to see increased momentum across all major dimensions of AMD business. Each AMD business unit is entering an exciting new product cycle ? from panel processors in the digital television space to high performance quad-core processors to a next generation notebook platform.

Below is a summary of key highlights and disclosures from the event.

Corporate priorities for AMD include the delivery of differentiated platform solutions, and high-end performance to the mainstream. The company is also working to achieve profitability in each of its businesses for 2008.

Computing products

The 2008-2009 roadmap for the computing products include the shipments of the updated Quad-Core AMD Opteron processors for Q108, while platforms from AMD OEM and system builder partners are expected in Q208.

"Montreal" will be AMD?s first octal-core server processor in 2009, and will be introduced in tandem with the first AMD server platform, codenamed "Piranha." In addition to featuring a new AMD server chipset, the "Piranha" multi-processor platform will feature HyperTransport 3.0 and DDR3 memory technology.

AMD detailed its first notebook APU, codenamed "Swift," and first APUbased notebook platform, codenamed "Shrike." "Swift" will use existing CPU core and GPU core technologies, integrated on a single silicon die.

The "Shrike" platform is planned to benefit from the faster data throughput and greater power efficiency of the "Swift" APU design to deliver richer graphics and longer battery life for users. AMD plans to ship "Swift" and "Shrike?"in time to enable customers to begin volume sales of "Shrike"-based platforms in second half 2009.

Graphics Products

AMD shared details about its transition to 55nm with a top-tobottom portfolio of graphics processors in early 2008. The company expects to achieve a multi-GPU leadership position with CrossFireX for enthusiasts and Hybrid Graphics for entry-level and mainstream users.

AMD also expects to achieve notebook discrete graphics design win leadership in 2008.

Consumer Electronics

AMD sees big opportunities for growth in its consumer electronics business. TV sales are rapidly shifting to LCD TVs with larger displays and higher resolutions that require better video quality; AMD's MPEG Video Processors as well as new products currently in the pipeline will deliver better image quality and performance, according to AMD.

Handset graphics technology is driving the user experience with the emergence of touch screen user interfaces; AMD offers 3-D graphics and hardware 2-D vector graphics.

Manufacturing Priorities

The company is on schedule for the ramp of 45nm in first half of 2008, with products in market during second half of 2008.

The AMD technology development alliance with IBM continues to deliver: First 32nm SRAMs were demonstrated; plan continues for 2010 introduction of 32nm parts.

Accelerated Computing

Accelerated Computing represents both an AMD vision for the industry as well as a set of internal AMD R&D initiatives to achieve that vision. It focuses on enabling the integration of differing on-system accelerator chips and on-silicon accelerator cores, in varying configurations, to achieve greater performance, higher energy efficiency and improved functionality.

Today, AMD's Accelerated Computing technology initiative is broken into three primary parts, with each sub-initiative focused on enabling one of the critical aspects of the overall Accelerated Computing vision: "Torrenza," "Fusion," and "Bedrock."

Accelerated Processing Units (APUs)

Primarily as a result of the AMD "Fusion" efforts, AMD will introduce a new category of microprocessor called the Accelerated Processing Unit (APU). APUs are individualized processor designs, mixing various combinations of CPU cores and accelerator cores, targeted at specific market segments.

The first generation of APUs are planned for release in second half 2009 and will be x86 processors that integrate one or more processor cores with one or more graphics processor cores, requiring little to no changes in existing programming models or the x86 ISA. Later, APU core diversity will increase, creating a nearly limitless variety of possible core and accelerator combinations, based on the specific priorities of the end-user segment.

"Bedrock" Internal AMD R&D Initiative

This foundational initiative involves enabling and driving industry-friendly definition and adoption of standardized programming models that allow an increasingly diverse set of accelerator cores, including the full compute power of general-purpose GPUs, to be used in mainstream platforms.

"Fusion" Internal AMD R&D Initiative

"Fusion" is a set of silicon and system design programs focused on enabling varying accelerator cores be integrated on-silicon. Conceptually, silicon-level acceleration is somewhat similar to system-level acceleration, however increasing levels of speed and efficiency can be achieved through on-chip integration.

The first Fusion"-based processor designs will primarily combine central processing unit (CPU) cores and graphics processing unit (GPU) cores on a single silicon die.

Processing and visualization benefits will be achieved through reduced distance and material between processing cores, and therefore overall reduced data latency at reduced power.

In the future, differing types of cores will be integrated into "Fusion"-based designs.

"Torrenza" Internal AMD R&D Initiative

"Torrenza" is a set of hardware and ecosystem development programs focused on enabling separate, purpose-built chips created by AMD or by third parties to be attached to an AMD motherboard. These discrete accelerators offload specific types of work from the processor and process it at higher speed and efficiency than the processor is capable of alone.
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