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Tuesday, April 03, 2007
 Spansion's Architecture, Combines MirrorBit NOR, ORNAND and Quad Flash Memory on a Single Die
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Message Text: MirrorBit Eclipse Architecture is expected to enable feature phones with high performance and lower costs.

Spansion today unveiled its MirrorBit Eclipse architecture that combines MirrorBit NOR, ORNAND and Quad Flash memory on a single die.

Compatible with existing chipsets, the MirrorBit Eclipse architecture can enable feature phones and multimedia portable devices with high performance and lower costs. Handset OEMs can save up to 30 percent or more on their handset memory subsystems bill of materials costs, while experiencing more flexibility in their designs, according to Spansion.

By taking advantage of the MirrorBit Eclipse architecture with its NOR interface and XIP (execute-in- place) approach, handset OEMs can reduce the amount of DRAM in the system. As a result of the MirrorBit NOR, ORNAND and Quad combination, performance improvements such as running code at blasting speeds and storing large amounts of multimedia content can be achieved on a single die. Additionally, the MirrorBit Eclipse architecture integrates a programmable microcontroller, which replaces the conventional state machine typically used in Flash memory and also supports built-in self test (BIST).

The company expects first silicon in Q3, and plans to sample 65nm MirrorBit Eclipse solutions built from 300mm wafers at its SP1 facility later this year.
 
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