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Friday, August 4, 2006
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Panasonic to Start Mass Production of 45nm SoC in 2008
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Matsushita Electric Industrial, and Renesas Technology announced that they have entered the full integration testing of a 45-nm SoC (system-on-chip) semiconductor manufacturing technology.
The process technology is the first in the industry to begin a full integration
into all wafer processes incorporating ArF (argon-fluoride) immersion scanners
with a numerical aperture (NA) of 1.0 or more. ArF immersion scanner is a
technology that increases resolution by filling the gap between the projection
lens and the wafer with liquid, thereby increasing the effective lens diameter.
The two companies started working on the joint 45-nm process development project
in October 2005 and have collaborated on previous generation process development
since 1998.
The current joint development project is scheduled to be completed in the middle
of 2007, with volume production targeted to begin in fiscal 2008. The new 45-nm
process will be used by both Matsushita and Renesas in manufacturing SoCs for
advanced mobile products and networked consumer electronics products. Besides the
advanced ArF immersion lithography, the companies plan to introduce other new
technologies as part of the development project, including introduced-strain
high-mobility transistors3 and ELK (K = 2.4) multilayer wiring modules. ELK
multilayer wiring module is a multilayer copper wiring technology using interlayer
insulation films with low relative permittivity.
The two companies first agreed to work together on the development of
next-generation SoC technology in 1998, even before the establishment of Renesas
Technology. The new project is part of the fifth stage of their collaboration,
which began in October 2005. The impressive record of completed joint-development
projects includes a 130-nm DRAM merged process in 2001, a 90-nm SoC process in
2002, a 90-nm DRAM merged process in 2004, and a 65-nm SoC process in 2005. |
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