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Monday, October 01, 2018
Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies

Cadence digital, signoff and custom/analog tools have achieved the latest DRM and SPICE certifications for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs.

Cadence announced that the corresponding process design kits (PDKs) are now available for download. The company says that there are multiple design projects underway with early 5nm customers.

Cadence delivered a fully integrated digital implementation and signoff tool flow, which has been certified by TSMC for the latest versions of the 5nm and 7nm+ processes. For the 7nm+ process, the Cadence full-flow includes the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution and Physical Verification System (PVS). For the 5nm process, the Cadence certified tools include the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution.

Cadence digital and signoff tools optimized for TSMC's 5nm and 7nm+ process provide EUV support at key layers and associated design rules. Some of the newest enhancements for the 5nm and 7nm+ process include via pillar-aware synthesis and feed forward guidance with the Genus Synthesis Solution as well as a pin-access control routing method for cell electromigration (EM) handling and statistical EM budgeting support.

The Cadence-certified custom/analog tools for the latest versions of the TSMC 5nm and 7nm+ process technologies include the Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF Option and Spectre Circuit Simulator, as well as the Virtuoso custom IC design platform, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso ADE Product Suite and Virtuoso Integrated Physical Verification System. The Layout-Dependent Effect (LDE) Electrical Analyzer is also certified for 7nm+.

The Virtuoso Advanced Node Platform methodology consists of features and functionality required for creating 5nm and 7nm+ designs including mixed-signal functional verification, reliability analysis and an accelerated custom placement and routing methodology. Cadence also introduced new features including end-to-end constraint support, dummy insertion and advanced MIMCAP support specifically for the 5nm process.

In addition to the tools certified for TSMC's 5nm and 7nm+ process technologies, the Liberate Characterization portfolio and the Liberate Variety Statistical Characterization Solution have been validated to deliver accurate Liberty libraries including advanced timing, noise and power models. The solutions utilized methods to characterize Liberty Variation Format (LVF) models, enabling accurate process variation signoff for low-voltage applications and to create EM models enabling signal EM optimizations and signoff.

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