The U.S. Defense Advanced Research Projects Agency (DARPA) will pour $100 million into two research programs to create the equivalent of a silicon compiler aimed at significantly lowering the barriers to design chips.
Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips.
First announced in June 2017, DARPA's Electronics Resurgence Initiative (ERI) is a multi-year, upwards of $1.5 billion investment in jumpstarting innovation and collaboration across the U.S. electronics community to address an array of long foreseen challenges to Moore's Law. To kickoff this community-wide effort, DARPA hosted its first annual ERI Summit from July 23-25 in San Francisco, CA. The three-day event brought together voices from across the electronics community - including Alphabet, Applied Materials, Intel, Synopsys, Cadence, Mentor Graphics, NVIDIA, and IBM - to address challenges and opportunities for the next half century of electronics progress.
To help foster the open communication and collaboration needed to develop new ERI funding opportunities, DARPA announced an expanded agenda for the ERI Summit with the addition of the ERI "What's Next" Technical Brainstorming Workshops. Each workshop will address targeted applications for specialized, next-generation hardware - specifically artificial intelligence (AI), hardware security, hardware emulation, and photonics.
Part of the part of the Electronics Resurgence Initiative (ERI), the two new
programs -- IDEAS and POSH -- will aim to combat the growing complexity and cost of designing chips, now approaching $500 million for a SoC. Essentially, POSH aims to create an open source library of silicon blocks, and IDEAS hopes to spawn a variety of open-source and commercial tools to automate testing those blocks and knitting them into SoCs and printed-circuit boards.
If successful, the programs will enable companies to design in relatively low volumes chips that would be prohibitive today. It could also open a door for designers working under secure regimes in the government to make their own SoCs targeting nanosecond latencies that are not commercially viable.
The projects are scheduled for an interim release in 2020 aimed at producing chips not fully optimized for power, performance and area. Final results are slated for 2022 and target quality comparable to traditional design teams.
The idea of a silicon compiler has been a Holy Grail for the semiconductor industry for decades. Initial goals for 2020 are modest at only 50% of potential power/performance/area in part because the goal is so ambitious.