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Friday, June 22, 2018
AMD Presents Modular Routing Design for Chiplet-based Systems

AMD engineers have presented a potential solution for overcoming data routing issues in "chiplets" - a concept in which bare ICs are interconnected on a larger slice of silicon.

A chiplet is actually an integrated circuit block that is part of a chip that consists of multiple of chiplets. In such chips, a system is subdivided into functional circuit blocks, called "chiplets", that are often reusable IP blocks.

The idea is that individual CPUs, memory, and other key systems can all be mounted onto a larger slice of silicon, called an active interposer, which is thick with interconnects and routing circuits.

The chiplet concept allows data to move faster and free and result to the creation of smaller, cheaper, and more tightly integrated computer systems. Chiplets would allow the industry to take a variety of system components and integrate them more compactly and more efficiently together.

Each chiplet has its own on-chip routing system. But when many chiplets are chiplet connected together, "traffic jam" issues could easily occur. Data should be routed in such way that the system resources will be able to deal with it without delays.

The solution was given by Gabriel Loh, Fellow Design Engineer at AMD. At the International Symposium on Computer Architecture earlier this month, Loh and his partners presented a potential solution to this impending problem. In a paper entitled "Modular Routing Design for Chiplet-based Systems", AMDs researchers described a new methodology for designing Chiplet-based Systems in a way that components can largely be independently designed, but when put together results in a properly functioning (in this case, with respect to NoC deadlock issues) system.

In essens, the reearchers are adding an intelligent network to the interposer that could lead to a big change in how systems are designed and what they can do.

The team found that deadlocks on active interposers basically disappear if you follow a few simple rules when designing on-chip networks. These rules govern where data is allowed to enter and leave the chip and also restricts which directions it can go when it first enters the chip.

Following these rules mean that everything else on the interposer-all the other logic chiplets, memory, the interposer's own network, everything- become just one node on the network. This means that engineers can design chiplets without having to worry about how the networks on other chiplets work or even how the network on the active interposer works.

AMD is already using passive interposers-silicon that contains interconnects but no network circuits- in its Radeon R9 series.

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