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Tuesday, November 28, 2017
Cadence Releases First PCI Express 5.0 Verification IP


Cadence has made availabile the first Verification IP (VIP) in support of the new PCI Express (PCIe) 5.0 architecture, driving early adoption of next-generation PCIe standard for server and storage applications.

The Cadence VIP incorporates TripleCheck technology, which lets designers complete functional verification of server and storage system-on-chip (SoC) designs based on the PCIe 5.0 specification, providing designers with confidence that designs can function as originally intended.

Cadence TripleCheck technology provides a verification plan with measurable objectives linked to the specification features and a comprehensive test suite with thousands of ready-to-run tests to ensure compliance with the specification. Additionally, designers have access to the Indago Protocol Debug App, which provides protocol-specific interactions between the design, the VIP and the testbench to find the root cause of any design bugs.



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