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Thursday, June 15, 2017
Samsung Ramps up 64-Layer V-NAND Memory Production


Samsung Electrics said Thursday it will start mass production of fourth-generation 64-layer, 256-gigabit (Gb) 3-bit multi-level-cell (MLC) V-NAND chips and expand its product portfolio.

Samsung said the fourth-generation V-NAND chips will be used in various products, including solid state drives (SSDs), embedded UFS memory and memory cards for servers, PCs and mobile customers.

The Samsung 64-layer 3-bit 256Gb V-NAND features a data transfer speed of 1Gbps, which is the fastest among currently available NAND flash memory. Also, the V-NAND has the industry's shortest page program time (tPROG) of 500 microseconds among NAND flash memory, which is about four times faster than that of a typical 10-nanometer (nm) class, planar NAND flash memory and approximately 1.5 times faster than that of Samsung's fastest 48-layer 3-bit 256Gb V-NAND flash.

The new 64-layer 256Gb V-NAND provides more than a 30 percent productivity gain, compared to the 48-layer 256Gb V-NAND that preceded it. In addition, the 64-layer V-NAND has a 2.5V input voltage for its circuits, which leads to approximately 30 percent greater energy efficiency than the 3.3 volts that 48-layer V-NAND used. Also, the reliability of the new V-NAND cell increased by about 20 percent compared to its predecessor.

Samsung enabled these improvements by tackling a diversity of challenges that appear in the advanced V-NAND manufacturing process. Chief among them were realizing multi-billion channel holes that penetrate several dozen layers of cell-arrays, and minimizing the loss of electrons from about 85.3 billion cells.

As the layers of cell arrays increase, the level of technological difficulty also increases, especially in making the channel holes homogeneous in their shape from the top to the bottom layer, and in properly dispersing the weight of all the layers to improve the stability of the channel holes.

Another challenge that Samsung overcame was to realize 64 layers of cell arrays based on 3D CTF (charge trap flash) structure and uniformly cover the inner side of each channel hole with an atomically thin, non-conductive substance. This led to the creation of smaller cells with improved performance and reliability.

The South Korean tech giant said it plans to expand the production of the 64-layer chips to take up more than half of the company's monthly production of NAND flash by the end of this year.



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