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Tuesday, December 6, 2016
TSMC And IBM Detail Their 7nm Progress At 2016 IEDM


TSMC and IBM has presented separate papers at the International Electron Devices Meeting (IEDM), describing their respective results nudging forward both Moore's law and extreme ultraviolet lithography (EUV).



IBM has been supporting the use of EUV while TSMC has been more conservative.

TSMC announced the smallest 6T SRAM to date in a process that it aims to put into risk production by April.

TSMC's 256-Mbit SRAM test chip has a cell density of 0.027 mm2 with full read/write capabilities down to 0.5 V. The node should provide up to a 40% speed gain, a 65% power reduction, and a 3.3x routed gate density increase compared to TSMC's 16FF+ process now in volume production.

Commenting on work using the 7-nm process to validate EUV TSMC's executives said that the next generation lithography provided "comparable patterning fidelity" and "comparable yield" to the conventional immersion steppers it will use in the commercial 7-nm process next year. TSMC already announced its plans to start using ASML's EUV equipment in its 5-nm node.

However, TSMC did not comment on how the 7-nm process compares to its 10-nm node or nodes from rivals such as Samsung. But the company said that it had reached 50% yields on its 7nm SRAM. That suggests it is on a path to have volume manufacturing in the process by late 2017.

IBM described the smallest FinFET made to date in a research device made with EUV. The company showed FinFETs with contacted poly pitch of 44/48 nm, a metallization pitch of 36 nm, and a fin pitch of 27 nm. One device included a source-to-drain contact opening of about 10 nm and a gate length of about 15 nm.

The IBM paper described EUV use at multiple critical levels in the middle and back-end of line, including M1 lines and novel metal interconnects, "greatly enhancing the printability and process simplification."

The 27-nm fin was made with a self-aligned quad patterning process using a 2x sidewall-image-transfer technique. IBM used self-aligned double patterning for making gates.

The transistors used cobalt rather than tungsten to reduce both line and vertical resistance.

The pitches on IBM?s research chip leapfrog the 56-nm gate pitch that Intel announced in August for its 10-nm process, claiming industry-leading density for the node it aims to have in production next year.

When Samsung announced its 10-nm process recently, it said that it would skip a version of 7 nm using today's immersion lithography. Instead, it said it will roll out 7 nm with EUV, targeting production before the end of 2018.

Globalfoundries has said that it developed its own 7-nm process using immersion steppers that will be in production in 2018.


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