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Monday, October 26, 2015
Oracle Breakthrough SPARC M7 Processor and Systems Design


Oracle today introduced an all-new family of SPARC systems built on the 32-core, 256-thread SPARC M7 microprocessor.

The systems feature Security in Silicon for intrusion protection and encryption; SQL in Silicon that delivers database efficiency.

The new SPARC M7 processor-based systems, including the Oracle SuperCluster M7 engineered system and SPARC T7 and M7 servers, are designed to integrate with existing infrastructure and include fully integrated virtualization and management for cloud. All existing commercial and custom applications will run on SPARC M7 systems unchanged with improvements in security, efficiency, and performance. In addition, SPARC M7 is an open platform that developers can utilize to create new software that takes advantage of Security in Silicon and SQL in Silicon capabilities.

SPARC M7 systems features

For the first time, Silicon Secured Memory adds real-time checking of access to data in memory to help protect against malicious intrusion and flawed program code in production for greater security. Silicon Secured Memory protection is utilized by Oracle Database 12c by default and is simple to turn on for existing applications. Oracle is also making application programming interfaces available for customization.

Oracle says that hardware-assisted encryption built into all 32 cores enables use without performance penalty. Runtime and data can be secured for all applications even when combined with wide key usage of AES, DES, SHA, and more. Existing applications that use encryption will be automatically accelerated by this new capability including Oracle, third party, and custom applications.

The new system also adds co-processors to all 32 cores in order to offload and accelerate important data functions, improving efficiency and performance of database applications. Critical functions accelerated by these new co-processors include memory de-compression, memory scan, range scan, filtering, and join assist. Offloading these functions to co-processors lowers memory utilization, and enables up to 10x better database query performance. Oracle Database 12c In-Memory option supports this new capability in the current release. In addition, this new functionality is slated to be available to advanced developers to build the big data analytics platforms.

Oracle claims that the new SPARC M7-based systems deliver performance superiority with world record results in over 20 benchmarks, in addition to database, middleware, Java, and enterprise applications.

The new SPARC M7 processor is the design center of the new line of SPARC M7 systems that scale from 32 to 512 cores, 256 to 4,096 threads and up to 8 TB of memory. Oracle’s SPARC M7 chip is a 4.1 GHz 32-core/256-thread processor. In addition, Oracle has improved every other aspect of the design compared to previous generation designs resulting in increased single-thread performance and reduced latency.

The M7 will go on sale Monday in new models of Oracle's T- and M-series servers, as well as an upgrade to the Oracle Supercluster, a pre-configured system for running the Oracle database.

SPARC M7 PROCESSOR SPECIFICATIONS

  • 32 SPARC V9 cores, grouped into eight core clusters.
  • Up to 256 hardware threads per processor; each core supports up to 8 threads.
  • Maximum frequency: 4.133 GHz.
  • Total of 64 MB L3 cache per processor. The L3 cache is fully shared and partitioned by core clusters. Each partition is 8-way set-associative, inclusive of all inner caches.
  • Total of 2 MB L2 instruction cache and 4 MB L2 data cache per processor. Each core cluster contains four cores sharing a single 256 KB L2 instruction cache. Each pair of two cores shares a single 256 KB L2 data cache.
  • 16 KB L1 instruction cache and 16 KB L1 data cache per core.
  • Dual-issue, out-of-order integer execution pipelines, one floating-point unit,and integrated cryptographic stream processing.
  • Sophisticated branch predictor and hardware data prefetcher.
  • Encryption instruction accelerators in each core with direct support for 15 industry-standard cryptographic algorithms plus random number generation: AES, Camellia, CRC32c, DES, 3DES, H, DSA, ECC, MD5, RSA, SHA- 1, SHA-224, SHA-256, SHA-384, SHA-512.
  • 20 nm process technology




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