Rambus Inc. and Toshiba Corporation announced that they will jointly demonstrate Toshiba's ASIC evaluation chip that incorporates Rambus's parallel logic interface codenamed Redwood.

This new evaluation chip is implemented on Toshiba's 90-nanometer ASIC process and is capable of running at speeds up to 6.4GHz, which is six times faster than processor busses available today. The chip is being used as a test vehicle for future customer platforms. The Redwood interface has been designed for high volume, cost-sensitive applications.

The Redwood parallel bus interface family addresses intra-board applications including processor, chipset and network chip connections. It is optimized for low latency and low power parallel bus applications, and enables high-pin bandwidth to reduce overall package, board, and system costs. Additionally, Redwood can be backwards compatible with existing LVDS-based standards such as HyperTransport, SPI-4 and RapidIO, allowing for easy integration into next-generation products. In order to achieve backwards compatibility, Redwood offers customers a range of frequency and voltage support.

Elements integrated into the Redwood technology include a 400MHz to 6.4GHz data rate range, low-voltage differential signaling, backwards compatibility with existing standards, FlexPhase adaptive timing circuit technology, and dynamic current and termination capabilities. Combined, all of these technologies allow Redwood to achieve up to 6.4GHz speeds for low-cost systems.