Monday, October 20, 2014
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
TDK Brings Wireless Charging To Electric Cars
Intel To Work With AT&T To Research Software Defined Networking
Intel Meegopad T01 Is A Bay Trail PC On HDMI Stick
Biostar Relases New iDEQ-T1 Compact Desktop
SK Telecom and Samsung Join Hands to Lead 5G Network Technology
Pantech Applied for Bankruptcy Protection In The US
Glonbalfoundries Buy IBM's Micorelectronics Business
Microsoft To Launch A Wearable Device Soon
Active Discussions
How to generate lots of different CDs quickly
Yamaha CRW-F1UX
help questions structure DVDR
Made video, won't play back easily
Questions durability monitor LCD
Questions fungus CD/DVD Media, Some expert engineer in optical media can help me?
CD, DVD and Blu-ray burning for Android in development
IBM supercharges Power servers with graphics chips
 Home > News > PC Parts > New Met...
Last 7 Days News : SU MO TU WE TH FR SA All News

Tuesday, November 19, 2013
New Methodology For Customized SoC Design Enables Higher Circuit Density


Fujitsu Semiconductor has developed a new design methodology that enables both the higher circuit density and the shorter development time, for 28nm SoC (System on a Chip) devices.

SoCs with 28nm process are required to have more and more functionality and performance, which drive the need for more circuits packed into the chip. Designing such SoCs is becoming increasingly complex and taking significantly longer development time, while addressing the power consumption is also becoming more challenging.

Fujitsu's new proprietary procedures have been implemented for estimating more layout-friendly floor plans, as well as for considering wiring routs and timing closure to optimize internal data buses. These steps will help minimize the "white space" in which no transistors are placed, and thus allow more circuits to fit in a chip.

The technology also automatically synthesizes the net list data for physical layout, without the need to manually change the logic design. This brings improved routability and ease of timing closure, resulting in less time required for final layout process, as well as even higher density integration.



Fujitsu says that incorporating the new methods can improve the circuit density by 33%, and reduce the time for final layout process to as short as one month. The company will integrate the method into its new Customized SoC Solutions, and will be available for the development of RTL-handoff SoCs for its customers.

Fujitsu will start accepting orders to develop SoCs using the new methodology in February 2014.




Previous
Next
Pioneer Unveils The CDJ-900NXS        All News        Salesforce.com and HP to Offer 'Superpod' To Enterprises
Goodreads and Kindle FreeTime Now Available on the Amazon Kindle Paperwhite     PC Parts News      Intel Announces "Thunderbolt Ready" Upgrade Program for PC Motherboards, Desktops and Workstation Computers

Get RSS feed Easy Print E-Mail this Message

Related News
Fujitsu Boosts Lineup of Smartphones and Tablets for the Enterprise
Fujitsu Develops Fast Recovery Process for Multiple Disk Failures
Fujitsu Relases New Extreme Series SSDs
Fujitsu, NTT, and NEC To Commercialize 400Gbps-class Optical Transmission Technology
Fujitsu, Panasonic Announce New Direction for Their Semiconductor Businesses
Fujitsu To Phase Out Chip Production
Fujitsu Technology Reduces Network Switches in Cluster Supercomputers
New Fujitsu ARROWS Tab Q335/K Tablet Coming In October
Fujitsu Buys Shares of Panasonic Information Technology Solutions
Fujitsu Launch New Enterprise Laptop PCs
Fujitsu Develops Record-Breaking 56 Gbps Receiver For Communications Between CPUs
Fujitsu Launches The ARROWS NX F-05F Smartphone

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2014 - All rights reserved -
Privacy policy - Contact Us .