TSMC, the world's largest dedicated semiconductor foundry, today released three silicon-validated Reference Flows within the Open Innovation Platform (OIP) that enable 16FinFET systems-on-chip (SoC) designs and 3D chip stacking packages.
Electronic Design Automation (EDA) vendors collaborated with TSMC to develop and validate all these flows through multiple silicon test vehicles.
The new Reference Flows are:
1. TSMC's 16FinFET Digital Reference Flow, providing technology support to address post-planar design challenges including extraction, quantized pitch placement, low-vdd operation, electromigration, and power management.
2. The 16FinFET Custom Design Reference Flow, offering full custom transistor-level design and verification including analog, mixed-signal, custom digital and memory.
3. The 3D IC Reference Flow, addressing emerging vertical integration challenges with true 3D stacking.
"These Reference Flows give designers immediate access to TSMC's 16FinFET technology and pave the way to 3D IC Through-Transistor-Stacking (TTS) technology," said TSMC Vice President of R&D, Dr. Cliff Hou. "Delivering our most advanced silicon and manufacturing technologies as early and completely as possible to our customers is a major milestone for TSMC and its OIP design ecosystem partners."
The 16FinFET Digital Reference Flow uses the ARM Cortex-A15 multicore processor as a validation vehicle for certification. It helps designers adopt the new technology by addressing FinFET structure related challenges of complex 3D Resistance Capacitance (RC) modeling and quantized device width. In addition, the flow provides methodologies for boosting power, performance and area (PPA) in 16nm, including low-voltage operation analysis, high-resistance layer routing optimization for interconnect resistance minimization, Path-Based Analysis and Graph-Based Analysis correlation to improve timing closure in Automatic Place and Route (APR).
The 16FinFET Custom Design Reference Flow enables custom design by addressing the complexity of 16FinFET process effects and provides methodologies for design compliance in 16nm manufacturing.
The 3D IC process produces significant silicon scaling, power and performance benefits by integrating multiple components on a single device. TSMC's 3D IC Reference Flow addresses integration challenges through 3D stacking. Key features include Through-Transistor-Stacking (TTS) technology; Through Silicon Via (TSV)/microbump and back-side metal routing; TSV-to-TSV coupling extraction.