Renesas has developed a design technology achieving improved signal transmission speeds and also achieving three times the signal wiring density of earlier Renesas products by combining multiple types of distributed impedance matching circuits in three dimensions in an ordinary ball grid array (BGA) type package substrate.
The purpose of this technology is to prevent the degradation of signal waveforms that occurs due to impedance differences (also referred to as impedance mismatch) between integrated circuits and the printed circuit boards on which they are mounted.
The primary feature of this technology is that it achieves the Optical Internet Forum (OIF) standard allowable signal reflection level of minus 8 dB. This will allow implementation of the soon to appear 16 Gbps class communication standard, such as PCI Express version 4, and will make 25 Gbps class data transfers possible. Furthermore, the efforts to achieve higher wiring density in signal lines incorporated in this technology will allow miniaturization of system ICs for routers and servers that perform high-speed multi-channel data transfers with as many as 100 channels and will also make its application to high-density packaging, such as SIP (system in a package), possible.
At the same time Renesas will, through this new technology, contribute to the miniaturization and increased performance of communication equipment. Also, Renesas believes that this technology contributes to achieving the inevitable smart society of the future, by processing, at even higher speeds the large volumes of data acquired at every second ("big data") from sensor networks formed from smart analog devices and from the smart power grid formed from equipment such as smart power meters.
Impedance is an electrical characteristics value that is determined by the IC itself and the structure, dimensions of the printed circuit board, and frequency dependencies. In a signal transmission circuit, when the impedances of the sending side and receiving side match, the energy (electrical signal) received by the receiver is maximized. When they do not match, the energy received by the receiver is reduced due to the occurrence of signal reflection. If the mismatch is particularly large, a phenomenon in which the signal is reflected along the transmission line and the signal waveform is disrupted occurs. Furthermore, as the communication speed increases, the impedance falls due to the chip pad capacitances, and the difference of the impedance between the chip pad and the wiring on the printed circuit board increases.
Previously, the method of reducing impedance difference by adding a single coil to each I/O channel on the chip was created to support speeds in the 12.5 Gbps class. This method, however, increases the size of the chip and the manufacturing costs. Alternatively, if the coils are fabricated using a process with a smaller feature size, the problem of increased susceptibility to electrostatic noise arises.
To resolve these issues, the technology of using special printed circuit boards into which passive components have been built in was invented, but, due to manufacturing reliability and cost issues, this technology has not yet reached the level of practical application.
Given this background, in 2008, Renesas announced, at the ECTC (IEEE Components and Technology Conference), a semiconductor package design technology conference, a distributed constant circuit-like impedance matching design method used in high-frequency areas as a means of reducing signal reflections due to impedance mismatching, and has used that technology in ICs that require high-speed data transfers. This technology makes aggressive use of the parasitic device components, such as the inductances and capacitances that are unavoidable in a multi-layer printed circuit board to canceled out reflected waves from electrical signals and minimize signal waveform degradation.
Renesas has further developed the technology announced at ECTC and achieves both higher signal speeds and higher densities at the same time by positioning multiple types of distributed impedance matching circuits so that they are closely packed.
Specifically, a multi-stage structure was adopted for the distributed impedance matching circuits to ensure a wide signal bandwidth of over 12.5 Gbps. Furthermore, in addition to separating two types of distributed impedance matching circuits of different sizes with through holes or vias into separate layers in the package, they were positioned to be filled with high density. This achieved a closely packed structure. Also, Renesas was able to achieve distributed impedance matching circuits that have about 3 times the signal density (as earlier Renesas products) and twice the signal bandwidth, by using the fact that these circuits have the same characteristics when the signal phase difference is 360 degrees, and performing distributed placement for these distributed constant circuits.
As a result of these developments, Renesas was able to clear the allowable signal reflection standard of minus 8 dB as standardized by OIF without adding additional circuits in the chip itself or adding any specialized fabrication steps to the package substrate.
Furthermore, Renesas is collecting these three dimensional distributed constant circuits consisting of vias, through holes, and interconnects into libraries for use as a design environment for efficient package design using this new technology. Using these three-dimensional distributed constant circuits provided in advance makes it possible to perform wiring design for package substrates in less than 1/1000 the time it would have using the earlier design method in which electromagnetic analysis was performed along with the design process.
Renesas is planning to aggressively expand their product line with application products using this newly-developed technology, in particular, not only moving from 12.5 Gbps class to the 25 Gbps class for backbone networks, but also considering devices applicable even to communication standards that perform data communication in the 16 Gbps class, such as the forthcoming PCI Express version 4 standard.