ARM on Monday announced at Computex an optimized IP
solution - the ARM Cortex-A12 processor, the Mali-T622
GPU, Mali-V500 video solution and POP IP technology -
designed to power mid-range mobile devices smartphones
The mid-range market is projected to exceed the number
of premium smartphones and tablets beginning in 2015.
Targeted at the mid-range market, this new suite of ARM
IP is optimized for power, performance and die size.
Used together, this suite of IP provides features like
virtualization, big.LITTLE processing and GPU compute at
mid-range price points.
The suite extends the ARM Cortex-A processor and ARM
Mali-T GPU series with the Cortex-A12 processor and
Mali-T622 GPU and introduces a new video IP product, the
Mali-V500. With support from ARM POP technology and the
ARM Development Studio 5 (DS-5) toolchain, ARM partners
can deliver smartphones and tablets with higher
efficiency and reduced time to market. ARM expects this
IP solution will be in mobile devices by mid-2014.
"Mobile users expect a range of devices at different
price points and for a mid-range mobile experience to
include some high end mobile features. With a billion
smartphones predicted to ship in 2013 and tablets
projected to out-ship notebook PCs, device-makers can
now provide quality, high-performance mobile products
with the features that matter the most, at a range of
price points," said Ian Drew, chief marketing officer
and executive vice president, ARM. "The market is
evolving at an amazing rate and there is now a choice of
solutions for semiconductor companies and for mobile
device-makers. Our suite of optimized IP expands the
choice for the mid-range mobile market."
The energy-saving technology known as ARM big.LITTLE
processing is only just coming to high-end devices
today, but now can be designed into mid-range
smartphones, allowing users to do more with their
devices. ARM claims that the Cortex-A12 processor offers
a 40 percent performance uplift in the same power
envelope when compared to the Cortex-A9 processor. The
Cortex-A12 processor builds on efficiency as a
standalone solution and additionally supports the
big.LITTLE processing technology with the Cortex-A7
processor. The Cortex-A12 also introduces features found
in premium smartphones and tablets to mid-range devices,
The Mali-T622 GPU, is OpenGL ES 3.0 conformant, supports
the Renderscript and OpenCL APIs, and is the smallest
full profile GPU Compute solution available for mobile
devices. It is also providing a 50 percent
energy-efficiency improvement over first-generation
Mali-T600 series products.
The Mali-V500 video solution provides dedicated video
processing and reduces system bandwidth requirements by
more than 50 percent compared to currently available
solutions. The Mali-V500 is a multicore video solution,
scaling from a single core capable of 1080p/60 encode
and decode to multiple cores supporting ultra-high
definition 4K at 120 frames per second. Additionally,
the Mali-V500 video solution was architected with
support for TrustZone security technology enabling
hardware-backed security for movie and TV content from
download to display.
ARM DS-5 toolchain to support development and
optimization of software for systems based on the
Cortex-A12 processor, Mali-T622 GPU, and CoreLink
CCI-400 cache coherent interconnect. Complemented by the
addition of the ARM Fast Models simulation library, the
DS-5 toolchain enables early software development and
system-wide performance and power optimization.
POP IP for the Cortex-A12 processor is available now for
TSMC 28HPM process technology. It will also be available
at GLOBALFOUNDRIES 28-SLP process technology in Q4 2013.
GLOBALFOUNDRIES claims that its 28nm-SLP process
technology and associated ARM POP IP for the Cortex-A12
processor enables up to 70 percent higher performance
(measured single-thread performance) and up to 2x better
power efficiency in comparison to a Cortex-A9 processor
using 40nm process technology. GLOBALFOUNDRIES'
next-generation 14nm-XM FinFET technology is expected to
bring another dimension of enhanced power, performance
and area for ARM mobile processors. A Cortex-A9
processor implemented on 14nm-XM technology, using
9-track libraries, is projected to enable a greater than
60 percent increase in frequency at constant power, or a
decrease of more than 60 percent in power consumption at
constant performance, when compared to implementation on
28nm-SLP technology using 12-track libraries. Similar
results are expected for Cortex-A12 processor
Intel has said it has managed to match ARM on battery life in smartphones and tablets with its current Atom processors, and will take the lead with its upcoming Atom chips based on the new Silvermont architecture.
But ARM executives dismissed that claim during at Computex in Taipei, saying the company's processor designs continue to offer more performance at low power consumption levels, and that it will continue to lead in battery life.
Intel Silvermont's power-saving features are generally attributed to Intel's the 22-nanometer manufacturing process, in which 3D transistors are stacked on top of one another (FinFET).
ARM-based chips do not have 3D transistor stacking features, although ARM is catching up on that, since chip manufacturers GlobalFoundries and TSMC are expected to implement 3D transistors in 2014 or 2015.
||1-4X SMP within a single processor cluster
Multiple coherent processor clusters through AMBA® 4 technology
TrustZone® security technology
NEON™ Advanced SIMD
DSP & SIMD extensions
VFPv4 Floating point
Hardware virtualization support
Large Physical Address Extensions (LPAE)
||ARMv7 Memory Management Unit
|Debug and Trace
|Cortex-A12 Processor Key Features
||Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store instructions
||Ensures reliable implementation of security applications ranging from digital rights management to electronic payment
||NEON technology can accelerate multimedia and signal processing algorithms such as video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image processing, telephony, and sound synthesis
|DSP & SIMD Extensions
||Increase the DSP processing capability of ARM solutions in high-performance applications, while offering the low power consumption required by portable, battery-powered devices. The DSP extensions are optimized for a broad range of software applications including servo motor control, Voice over IP (VOIP) and video & audio codecs.
||Hardware support for floating-point operations in half-, single- and double-precision floating point arithmetic. The floating-point capabilities of the Cortex-A12 processor offer increased performance for floating point arithmetic used in next generation mobile devices
||Highly efficient hardware support for data management and arbitration, whereby multiple software environments and their applications are able to access simultaneously the system capabilities. This enables the realization of devices that are robust, with virtual environments that are well isolated from each other.
|Large Physical Address Extensions (LPAE)
||The introduction of Large Physical Address Extensions (LPAE) enables the processor to access up to 1TB of memory.
|Optimized Level 1 Caches
||Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption. Caches are configurable size 32kB – 64kB for instruction, and 32kB for data. Also providing the option for cache coherence for enhanced inter-processor communication or support of rich SMP capable OS for simplified multicore software development
|Integrated, Configurable Size Level 2 Cache Controller
||Providing low latency and high bandwidth access to up to 8 MB of cached memory in high frequency designs, or design needing to reduce the power consumption associated with off chip memory access.
||This AMBA® 4 AXI™ compatible master interface allows for low-latency accesses to peripherals effectively eliminating any traffic congestion between transactions going to peripherals and main memory resulting in higher overall performance.
|Accelerator Coherency Port (ACP)
||This AMBA® 4 AXI™ compatible slave interface allows an external master to participate in the cache coherency mechanism of the Cortex-A12 processor which reduces the overhead of performing coherency maintenance in software.
|Cortex-A12 Companion IP
|AMBA 4 Cache Coherent Interconnect (CCI-400)
Efficient voltage scaling and power management is enabled with the CoreLink ADB-400 unlocking DVFS control of the Cortex-A12 processor. Further 'extension' of the DVFS curve also comes when used with the Cortex-A7 processor.
- The CCI-400 provides AMBA® 4 AXI™ Coherency Extensions (ACE) compliant ports for full coherency for The Cortex-A12 processor and other Cortex processors, better utilizing caches and simplifying software development. This feature is essential for high bandwidth applications including future mobile SoCs that require clusters of coherent processors or GPUs. Combined with other available ARM CoreLink™ System IP, the CCI-400 increases system performance and power efficiency.
- CoreLink CCI-400 Cache Coherent Interconnect provides system coherency with Cortex processors and an IO Coherent channel with Mali IP and opens up a number of possibilities for offload and acceleration of tasks. When combined with a Cortex-A7 processor, CCI-400 allows big.LITTLE operation with full L2 cache coherency between the Cortex-A12 and Cortex-A7 processors.
|AMBA Generic Interrupt Controller (GIC-400)
||AMBA Interrupt Controllers like the GIC-400 provide an efficient implementation of the ARM Generic Interrupt Specification to work in multi-processor systems. They are highly configurable to provide the ultimate flexibility in handling a wide range of interrupt sources that can control a single CPU or multiple CPUs.
|AMBA 4 CoreLink MMU-500
||CoreLink MMU-500 provides a, hardware accelerated, common memory view for all SoC components and minimizes software overhead for virtual machines to get on with other system management functions.
||The Cortex-A12 processor also enjoys a secure, optimized path to memory to further enhance its market leading performance with the aid of CoreLink TZC-400 TrustZone® address space controller
||All interconnect components and the ARM DMC guarantee bandwidth and latency requirements by utilizing in-built dynamic QoS mechanisms.
||ARM CoreSight™ SoC debug and trace hardware is used to profile and optimize the system software running through-out from driver to OS level.
|4x Full Scene Anti-Aliasing (FSAA) with minimal performance drop
||OpenGL® ES 1.1, 2.0, 3.0
|Full support for next-generation and legacy
2D/3D graphics applications
||Compatible with a wide range of bus
interconnect and peripheral IP
||32KB recommended per core
||Built-in Memory Management Unit (MMU) to support virtual memory
||1 to 2 cores
||A single IP covering a range of mid to high-end product requirements and price/performance points
|Adaptive Scalable Texture Compression
||Low dynamic range (LDR) and high dynamic range (HDR). Supports both 2D and 3D images
||ASTC offers a number of advantages over existing texture compression schemes by improving image quality, reducing memory bandwidth and thus energy use.
||For encode: H.264, VP8 For decode: H.264, H.263, MPEG4, MPEG2, VC-1/WMV, Real, VP8
||Driver and video streaming infrastructure based on OpenMAX™ which runs on the host CPU
||AMBA3 AXI or AMBA 4 ACE Lite
||Compatible with a wide range of bus interconnect and peripheral IP
||Built-in Memory Management Unit (MMU) to support virtual memory
||A single core clocked at 600MHz is capable of 1080p60 decoding or encoding
||1080p60 to 4k120* [*2160p]
||Scalable from one to eight cores with multiple performance points