Friday, May 26, 2017
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
NVIDIA Introduces New GeForce GTX Battlebox
TSMC is Already Testing 7nm Chips, Coming Next Year
Microsoft's Beam Streaming Service Becomes "Mixer"
Lenovo Returns to Profitability
RICOH WG-50 Waterproof Digital Compact Camera Released
Acer Announces New Nitro 5 Notebook Line, Entertainment-Oriented Tablet and the Spin 1 Convertible
Google's Alpha Go Beats Chinese Master Again
Kingston KC1000 NVMe PCIe SSD Meets Demanding Data Needs of SSD Enthusiasts
Active Discussions
Which of these DVD media are the best, most durable?
How to back up a PS2 DL game
Copy a protected DVD?
roxio issues with xp pro
Help make DVDInfoPro better with dvdinfomantis!!!
menu making
Optiarc AD-7260S review
cdrw trouble
 Home > News > Mobiles > Toshiba...
Last 7 Days News : SU MO TU WE TH FR SA All News

Friday, February 22, 2013
Toshiba Develops Low Power Technology for Embedded SRAM


Toshiba has developed an innovative low-power technology for embedded SRAM for application in smart phones and other mobile products.

The new technology reduces active and standby power in temperatures ranging from room temperature (RT) to high temperature (HT) by using a bit line power calculator (BLPC) and a digitally controllable retention circuit (DCRC). A prototype has been confirmed to reduce active and standby power consumption at 25C by 27% and 85%, respectively.

Typically, longer battery life requires lower power consumption in both high performance and low performance modes (MP3 decoding, background processing, etc.). As low performance applications require only tens of MHz operation, SRAM temperature remains around RT, where active and leakage power consumptions are comparable. Given this, the key issue is to reduce active and standby power from HT to RT.

Toshiba's new technology applies a BLPC and DCRC. The BLPC predicts power consumption of bit lines by using replicated bit lines to monitor the frequency of the ring oscillator. It minimizes the active power of the SRAM in certain conditions by monitoring the current consumption of the SRAM rest circuits. The DCRC decreases standby power in the retention circuit by periodically activating itself to update the size of the buffer of the retention driver.

Toshiba presented this development at the 2013 IEEE International Solid-State Circuit Conference in San Francisco, CA on February 20.


Previous
Next
PayPal Brings Mobile Payments To Europe        All News        OCZ Bundles Far Cry 3 PC Game With Its Vector SSD Series
Mobile World Congress Kicks Off On Monday     Mobiles News      Next LG Optimus G II To Use ARM-based Chips Developed In-house

Get RSS feed Easy Print E-Mail this Message

Related News
Western Digital Raises its Offer For Toshiba's Memory Business: report
Broadcom, KKR and SK Hynix - Bain Join Final Bidding Round for Toshiba's Memory Unit
Western Digital Takes Legal Action Against Toshiba to Block Sale Of Memory Chip Business
Toshiba Tells Western Digital To Stop Messing Up With Chip Unit Sale
Toshiba Demonstrates 64-Layer BiCS FLASH on Client NVM Express SSD
Toshiba to Spin Off 4 Operations
Questions Remain About The Fate Of Toshiba's HDD and SSD Business
Toshiba's Shareholders Seek For New Compensatory Damages
Toshiba's New 8TB Consumer Hard Disk Focuses on Reliability
INCJ Added to the List Of Companies Interested In Toshiba's Chip Unit
Apple Eyes Toshiba's Memory Chip Business: reports
Toshiba To Sell Its TV Business, Turkish, Chinese Companies Among Buyers

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2017 - All rights reserved -
Privacy policy - Contact Us .