ARM today announced the availability of a
power-optimized quad-core hard macro implementation of
its flagship ARM Cortex-A15 MPCore processor.
The ARM Cortex-A15 MP4 hard macro is designed to run at
2GHz and delivers performance in excess of 20,000DMIPS,
while maintaining the power efficiency of the Cortex-A9
hard macro. The Cortex-A15 hard macro development is the
result of the synergy arising from the combination of
ARM Cortex processor IP, Artisan physical IP, CoreLink
systems IP and ARM integration capabilities, and
utilizes the TSMC 28HPM process.
ARM claims that the low leakage implementation,
featuring integrated NEON SIMD technology and floating
point (VFP), delivers a balance of performance and power
and is ideal for wide array of high-performance
computing applications for such as notebooks through to
power-efficient, performance-orientated network and
enterprise devices.
The hard macro was developed using ARM Artisan 12-track
libraries and the recently announced Processor
Optimization Pack (POP) solution for the Cortex-A15 on
TSMC 28nm HPM process.
Full configuration and implementation details will be
presented at the Cool Chips conference (18-20 April) in
Yokohama, Japan.