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 Home > News > General Computing > ARM Rel...
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Monday, April 16, 2012
ARM Relases Processor Optimization Pack Solutions for TSMC 40nm and 28nm Process Variants


ARM today announced the availability of an expanded lineup of ARM Processor Optimization Pack (POP) solutions for TSMC 40nm and 28nm process technologies targeting a range of ARM Cortex processors.

At least nine new POP configurations targeting Cortex-A5, Cortex-A7, Cortex-A9 and Cortex-A15 processor cores will be released. POPs enable ARM partners to quickly close timing of single-, dual- and quad-core implementations across a broad envelope of power, performance and area optimization points.

At the 28nm HPM (high performance for mobile) and 28nm HP (high performance) process variants, ARM is launching new POPs for the Cortex-A9 core as well as the first POPs for ARM's newest Cortex-A7 and Cortex-A15 processors. Since the Cortex-A7 and Cortex-A15 cores are used in tandem as ARM's big.LITTLE processing solution, the addition of POPs for both cores assures a complete solution for big.LITTLE implementations. ARM's licensee for the Cortex-A15 POP for TSMC 28nm HPM is progressing toward the tape out of its first chip in the coming months.

At TSMC 40nm LP (low power), ARM?s existing POP offering for the Cortex-A5 and Cortex-A9 processors is being augmented with the new Cortex-A7 POP. In addition, working in concert with TSMC, ARM will offer new POP variants supporting the latest options for TSMC 40nm LP, so those process options can take full advantage of the POP implementation benefits. ARM?s POPs for TSMC 40nm LP for Cortex-A5 (1.0 GHz) and Cortex-A9 (1.4 GHz) are shipping in production chips by ARM partners in such applications as smart-TV, set-top box, mobile computing and smart phones.

A Processor Optimization Pack solution is composed of three elements necessary to achieve an optimized ARM core implementation. First, it contains ARM Artisan Physical IP logic libraries and memory instances that are specifically tuned for a given ARM core and process technology. This Physical IP is developed through a tightly coupled collaboration with ARM processor engineers in an iterative process to identify the optimal results. Second, it includes a comprehensive benchmarking report to document the exact conditions and results ARM achieved for the core implementation. Finally, it includes a POP Implementation Guide that details the methodology used to achieve the result.


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