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Saturday, February 25, 2012
First 28nm ARM Cortex-A9 Processor Optimization Pack Available for GLOBALFOUNDRIES 28nm-SLP HKMG Process

ARM has announced the availability of the ARM Cortex-A9 MPCore Processor Optimization Pack (POP) for GLOBALFOUNDRIES' 28nm-SLP High-K Metal Gate process technology.

Optimized for mobile, networking and enterprise applications, the ARM POP 28nm-SLP for Cortex-A9 processors delivers a performance range from 1GHz to 1.6GHz for worst case conditions, with up to 2GHz in typical conditions. This provides flexibility for System-on-Chip (SoC) designers to optimize performance and energy-efficiency using the ARM Artisan Physical IP Platform and Cortex-A9 POP.

"As consumer demand for high-performance, energy-efficient mobile devices increases, GLOBALFOUNDRIES and ARM are lowering the risk for customers by delivering optimized Cortex-A9 cores on a proven 28nm SoC process," said Kevin Meyer, Vice President of Design Enablement Strategy and Alliances, GLOBALFOUNDRIES. "This latest ARM physical IP solution for our 28nm-SLP process delivers industry-leading performance and energy-efficiency, while also decreasing time to market for customers' latest mobile products."

GLOBALFOUNDRIES' 28nm Super Low Power (SLP) platform is designed for power-sensitive mobile and consumer applications, and is based on the company?s 32/28nm HKMG technology. ARM already supports the GLOBALFOUNDRIES 28nm-SLP process with a Artisan Physical IP Platform. This includes process tuned 9 track and 12 track multi-Vt standard cell libraries, power management kits, ECO kits, ARM Artisan high-density optimized memory compilers, as well GPIO through the ARM DesignStart online IP access portal.

ARM POPs include three critical elements necessary to achieve an optimized ARM core implementation. First, it contains Artisan Physical IP logic libraries and memory instances that are specifically tuned for a given ARM core and process technology. This Physical IP is developed through a collaboration with ARM Processor Division engineers in an iterative process to identify the optimal results. Second, it includes a benchmarking report to document the exact conditions and results ARM achieved for the core implementation. Finally, it includes a POP Implementation Guide that details the methodology used to achieve the result.

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