Intel will present its research efforts to deliver more power efficient processors and digital RF capabilities at the International Solid State Circuits Conference. The company will also also give public disclosures of the next-generation 22nm Ivy Bridge processor.
Topics at the conference include eaps in energy-efficient computing, integrated digital radio and SoC technology, efficient processor graphics and 22nm 3-D Tri-gate transistors.
Most of the papers that will presented are detailing Intel's research work using its new 22 nm tri-gate process technology. The company will describe techniques to deliver five- to ten-fold power efficiency gains by driving circuits to perform at near threshold voltage levels.
Intel Claremont processor is a research chip running at such low voltages it could be powered up by a handheld solar cell. Intel aims to explore how low it can go in getting work out of chips at the lowest power levels. At ISSCC, Intel will give an an overview of the chip layout, design methodology, etc. The chip is built in low-leakage 32nm SoC technology, it operates from 280mV @ 3MHz to 1.2V @ 915MHz. Intel claims that it offers 4.7x better energy efficiency in near-threshold voltage (NTV) mode and it has a 2mW minimum power. The company will also describe an effort using similar techniques for a bank of 22 nm eight-transistor SRAMs used as a CPU cache.
A paper will detail a 256-bit wide SIMD graphics block made in a 22 nm process operating at 280 millivolts for a 9x efficiency gain.
Separately, Intel will present papers on advances in digital processing in RF, focused mainly on work in 2.4 GHz Wi-Fi.
Another paper describes Rosepoint, the first 32nm SoC with a 2.4 GHz WiFi RF transceiver and two 32nm Atom cores on the same die. Commercial versions of such chips could emerge by mid-decade as standalone digital RF transceivers.
Additional Intel papers at ISSCC 2012 include:
- A 22nm IA Multi-CPU and GPU System-on-Chip
- A 2.05G Vertices/s 151mW Lighting Accelerator for 3D Graphics in 32nm CMOS
- A 4.6GHz 162Mb SRAM in 22nm CMOS With Integrated Active VMIN-Enhancing Assist Circuitry
- A 32nm CMOS All-Digital Reconfigurable Fractional Freq. Divider for Multistandard SoC Radios
- A Reconfigurable Distributed All-Digital Clock Generator Core in 22nm High-k Tri-Gate LP CMOS
- A TDC-Less ADPLL With 200-to-3200MHz Range for Mobile SoC Clocking in 22nm CMOS
- Ratiometric BJT-Based Thermal Sensor in 32nm and 22nm Technologies
Intel's full list of papers that will be presented at the conference is available here
. The 2012 IEEE International Solid-State Circuits Conference (ISSCC) will be held in San Franscisco, Feb. 19-23, 2012