Tuesday, July 25, 2017
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
Razer Tiamat Flagship Headsets Released
Adobe Pulls Plug on Flash Player
Burn-in Warranty for Samsung QLED TV Screens Extended to 10 Years
New USB 3.2 Update Doubling Bandwidth to Extend USB Type-C Cable Performance
New Motorola Z2 Force Edition Comes With 360-degree Camera Mod
Huawei Holds First Place, Xiaomi Climbs to Fourth in Chinese Smartphone Shipments
Google Adds SOS Alerts to Search and Maps
Porsche Design's Huawei Watch 2 Costs $925
Active Discussions
Which of these DVD media are the best, most durable?
How to back up a PS2 DL game
Copy a protected DVD?
roxio issues with xp pro
Help make DVDInfoPro better with dvdinfomantis!!!
menu making
Optiarc AD-7260S review
cdrw trouble
 Home > News > General Computing > Toshiba...
Last 7 Days News : SU MO TU WE TH FR SA All News

Wednesday, November 16, 2011
Toshiba Develops Circuit Techniques for Power-efficient Embedded SRAM


Toshiba has developed circuit techniques for embedded SRAM that operate in a wide supply voltage range, from 0.5V to 1.0V, which effectively contribute to lower power consumption of electronic devices.

The test chip fabricated employs three new techniques to ensure proper operation of SRAM even when the operating voltage varies. At the same time, cell failure rate is reduced and fast operation is achieved. Toshiba has demonstrated these techniques in a 40nm 2Mb SRAM test chip at 0.5V operation. This achievement was reported today at the IEEE Asian Solid-State Circuits Conference (A-SSCC) 2011, now being held in South Korea.

The chip employs three new techniques to achieve stable operation even when the voltage varies or is low.

Embedded SRAM in LSI for mobile equipment have multiple cells for data storage and must achieve stable performance even if cell characteristics vary. Conventional SRAM techniques employ wordline selection signals for read/write operations. As operating conditions, such as transistor thresholds, temperature and voltage, vary, the optimum wordline voltage at which SRAM cells properly operate also changes. Toshiba's new circuit technique predicts SRAM cell failure rate in real time and automatically programs wordline voltage so that the cell memory is retained even when operating conditions vary. The result is a reduction in the cell failure rate to one-hundredth that of conventional SRAM. This new circuit technique also eliminates the need to program the wordline level voltage chip by chip, which conventional SRAM require.

When sense amplifier activation timing is adjusted to the slowest cell in low-voltage operation, it becomes too slow in high-voltage operation and SRAM performance slows. The new technique controls wordline voltage so that the voltage characteristics of the control circuit, which determines the sense amplifier activation timing, match the slowest cell's voltage characteristics. Consequently, activation at the optimum timing is possible at any operating voltage. This technique improves the activation timing in high-voltage operation even if the sense amplifier activation timing is optimized at the lowest operating voltage, resulting in an 18% improvement in operating frequency.

Another issue is an increased malfunction rate for SRAM cells affected by bit lines in read/write operations at low voltage, such as below 0.7V. Whereas the conventional technique selects wordlines one by one, the new technique simultaneously activates eight wordlines to read/write the same data, achieving operation at voltage as low as 0.5V, although available memory capacity is reduced.

These three new techniques realize embedded SRAM capable of operating in a wide voltage range. Power consumption at 0.5V operation is 57% less than that of conventional SRAM.


Previous
Next
Facebook Users Hit With Porn Videos        All News        HP Enters Ultrabook Market With Slim $900 Laptop
Facebook Users Hit With Porn Videos     General Computing News      Apple Names Arthur Levinson Chairman of the Board

Get RSS feed Easy Print E-Mail this Message

Related News
Toshiba Resumed Blocking Western Digital Access to JV Database
Court Says Western Digital Should Have Access Toshiba's Technical Databases
Toshiba in Talks with Western Digital, Foxconn Over Memory Unit Sale
Western Digital Responds to Toshiba's Actions
Toshiba Delays Chip Unit Deal, Sues Western Digital
Western Digital Resubmits Bid for Toshiba Chip Unit
Toshiba Chip-Unit Final Agreement Said to be Delayed, WD Opposes Participation of SK Hynix
Toshiba Open to Further Talks With Western Digital About Chip Unit Sale
Japan-led Consortium Wins Toshiba Memory Bidding
Toshiba Applies Spintronics Technology to Strain-gauge Sensor Element to Boost Sensitivity
Western Digital's SanDisk Subsidiaries Seek Injunctive Relief Against Toshiba in the Superior Court of California
Toshiba Faces New Lawsuit Over Accounting Scandal

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2017 - All rights reserved -
Privacy policy - Contact Us .