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Tuesday, August 30, 2011
GLOBALFOUNDRIES Announces Design Enablement Support for 20nm Design Flows


GLOBALFOUNDRIES has succesfully taped out a test chip based on its 20 nanometer (nm) manufacturing process.

The company announced that it has taped out a test chip using flows from EDA vendors Cadence Design Systems, Magma Design Automation, Mentor Graphics Corporation, and Synopsys Inc., demonstrated its readiness to begin evaluating its customer's 20nm designs.

"We are committed to providing customers as much of a time-to-market advantage as possible with each new technology we introduce," said Mojy Chian, senior vice president of design enablement at GLOBALFOUNDRIES. "Our model of early collaboration with EDA partners accelerates the overall development cycle, and gives customers accessibility to the inner workings of the process so they can begin targeting their designs to the most advanced manufacturing capabilities with confidence. This success is a major achievement toward market readiness of our newest process, and we will continue to enhance the design enablement support available for it."

All four EDA companies have demonstrated that their place-and-route (P&R) tools and tech files are capable of supporting the advanced rules associated with the 20nm process. The flows include library preparation steps for double patterning technology, a complex lithography approach that raises new challenges for designers at 20nm and beyond. The 20nm test chip requires double patterning and was implemented with each EDA partner contributing a large placed and routed design. Prior to tape out, each design was validated by GLOBALFOUNDRIES and checked against 20nm sign-off verification decks.

"Extensive 20nm collaboration with each EDA partner resulted in all designs being closed rapidly for a successful tapeout," GLOBALFOUNDRIES said.

In addition to demonstrating full support for all of the key steps in a 20nm P&R flow?including double patterning library preparation, placement, clock tree synthesis, hold fixing, routing and post route optimization - GLOBALFOUNDRIES worked with each of the EDA suppliers to include the necessary setup and support for technology and mapping files. The flow will also demonstrate foundry support for extraction, static timing analysis and physical verification.

GLOBALFOUNDRIES plans to make the design, libraries, and complete vendor flow scripts available to its customers who wish to evaluate the 20nm technology.

Collaboration withG Amkor

GLOBALFOUNDRIES also announced that is has entered into a strategic partnership with Amkor Technology, Inc. to develop integrated assembly and test solutions for advanced silicon nodes.

The companies plan to collaborate to co-develop and commercialize integrated fab-bump-probe-assembly-test solutions aimed at multiple customers and end-market applications and expand their lead-free bump licensing relationship.

Through the partnership, Amkor would become a founding member of GLOBALFOUNDRIES' new Global Alliance for Advanced Assembly Solutions, which is designed to accelerate innovation in semiconductor interconnect, assembly and packaging technologies.

Amkor and GLOBALFOUNDRIES have also recently expanded their prior lead-free wafer bump licensing relationship by amending their existing lead-free bumping technology license agreement.


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