Saturday, September 05, 2015
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
Facebook Dominates The Smartphone Apps Market
Toyota To Invest $50 million In Research Centers For Self-driving Cars
Report Reveals the Web's Shadiest Neighborhoods
Google Play Is Coming Back To China: report
Hackers Stole Data From Bugzilla
BlackBerry To Buy Rival Good Technology
GIGABYTE Z170X-UD5 Motherboard Is Intel Thunderbolt 3 Certified
LG Bets On OLED's Success, Showcases Innovative Prototypes At IFA2015
Active Discussions
How to back up a PS2 DL game
Copy a protected DVD?
roxio issues with xp pro
How to burn a backup copy of The Frozen Throne
Help make DVDInfoPro better with dvdinfomantis!!!
Copied dvd's say blank in computer only
menu making
Optiarc AD-7260S review
 Home > News > PC Parts > Rambus ...
Last 7 Days News : SU MO TU WE TH FR SA All News

Wednesday, June 15, 2011
Rambus Develops Clocking Technology for Power Reduction in High-Speed Interfaces


Rambus today announced the development of a fast power-on, low-power clocking technology that can enable a whole new class of memory devices.

Implemented in a 40nm low-power CMOS process, this technology is capable of transitioning from a zero-power idle state to a 5+ Gb/s data transfer rate in 5 nanoseconds (ns) while achieving active power of only 2.4mW/Gb/s.

In order to improve the energy efficiency of servers and mobile systems, system designers are continually looking for ways to reduce the energy required by the memory subsystem. Memories typically used in today's server applications are challenged to cycle in and out of the lowest power operating state rapidly. In mobile systems, which support a wide range of power modes, low power operation is usually accomplished through use of complex power state circuits. With this approach, developed by Rambus Labs, a feed-forward architecture is used to achieve extremely fast turn-on and turn-off, simplifying the system design and significantly reducing the overall system power requirements.

"Through this work, we've dramatically reduced system complexity and have saved substantial power while increasing performance to more than 5Gb/s per differential link," said Jared Zerbe, technical director at Rambus. "When incorporated into an SoC-to-memory interface, or SoC-to-SoC link, this development can significantly reduce the memory system power and time-to-first access, driving us closer to the vision of energy proportional computing."

Mr. Zerbe unveiled the results of this development today at the VLSI Circuit Symposium 2011 in Kyoto Japan.


Previous
Next
Music Unlimited powered by Qriocity App Available on Android Market        All News        Details On Google's Nexus 4G Emerge
AMD Launches Contest for Developers to Create Heterogeneous Compute Applications     PC Parts News      Intel's SSD 710 and 720 Series Specifications Leak

Get RSS feed Easy Print E-Mail this Message

Related News
Rambus To Start Selling Own Server Chips
Rambus and SK Hynix Extend Their License Agreement
Rambus Develops R+ DDR4/3 PHY on Samsung 28nm LPP Process
Rambus Signs License Agreement with Qualcomm
Rambus and Nanya Sign Patent License Agreement
Rambus CMOS Sensor Fits In Cameras Without Lens
Rambus Signs Agreement with Samsung
Rambus Settles Patent Disputes With Micron
Rambus Signs Agreement with STMicroelectronics
Rambus and SK Hynix Sign Patent License Agreement
Rambus Pleased With Court Ruling In SK Hynix Case
Rambus Demonstrates the Imerz IPTV Multi-Media Platform, Binary Pixel Technology at MWC

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2015 - All rights reserved -
Privacy policy - Contact Us .