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Wednesday, June 15, 2011
Rambus Develops Clocking Technology for Power Reduction in High-Speed Interfaces


Rambus today announced the development of a fast power-on, low-power clocking technology that can enable a whole new class of memory devices.

Implemented in a 40nm low-power CMOS process, this technology is capable of transitioning from a zero-power idle state to a 5+ Gb/s data transfer rate in 5 nanoseconds (ns) while achieving active power of only 2.4mW/Gb/s.

In order to improve the energy efficiency of servers and mobile systems, system designers are continually looking for ways to reduce the energy required by the memory subsystem. Memories typically used in today's server applications are challenged to cycle in and out of the lowest power operating state rapidly. In mobile systems, which support a wide range of power modes, low power operation is usually accomplished through use of complex power state circuits. With this approach, developed by Rambus Labs, a feed-forward architecture is used to achieve extremely fast turn-on and turn-off, simplifying the system design and significantly reducing the overall system power requirements.

"Through this work, we've dramatically reduced system complexity and have saved substantial power while increasing performance to more than 5Gb/s per differential link," said Jared Zerbe, technical director at Rambus. "When incorporated into an SoC-to-memory interface, or SoC-to-SoC link, this development can significantly reduce the memory system power and time-to-first access, driving us closer to the vision of energy proportional computing."

Mr. Zerbe unveiled the results of this development today at the VLSI Circuit Symposium 2011 in Kyoto Japan.


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