NEC and Tohoku University have developed of the world's first content addressable memory (CAM) that both maintains the same speed and non-volatile operation as existing circuits when processing and storing data on a circuit while power is off.
Content-addressable memory (CAM) is a special type of computer memory used in certain very high speed searching applications. It is also known as associative memory, associative storage, or associative array.
Unlike standard computer memory (random access memory or RAM) in which the user supplies a memory address and the RAM returns the data word stored at that address, a CAM is designed such that the user supplies a data word and the CAM searches its entire memory to see if that data word is stored anywhere in it. If the data word is found, the CAM returns a list of one or more storage addresses where the word was found (and in some architectures, it also returns the data word, or other associated pieces of data).
Because a CAM is designed to search its entire memory in a single operation, it is much faster than RAM in virtually all search applications. There are cost disadvantages to CAM however. Unlike a RAM chip, which has simple storage cells, each individual memory bit in a fully parallel CAM must have its own associated comparison circuit to detect a match between the stored bit and the input bit. Additionally, match outputs from each cell in the data word must be combined to yield a complete data word match signal. The additional circuitry increases the physical size of the CAM chip which increases manufacturing cost.
NEC's new CAM is a part of spintronics logic integrated circuit technologies that utilize the negative properties of electrons together with the spin magnetic moment (a small magnetic disposition which electron has negative charged particle). The new CAM utilizes the vertical magnetization of vertical domain wall elements in reaction to magnetic substances in order to enable data that is processing within the CAM to be stored on a circuit without using power. This contrasts to conventional technologies that required data to be stored within memory. As a result, data can be saved on circuits even when power is cut from the CAM.
In recent years, the use of Information and communication technologies (ICT) equipment has steadily increased due to the widespread growth of cloud computing. Most existing equipment requires a short amount of time to get started and internal circuits remain active when the equipment is in standby mode, consuming power.
Using the new CAM in combination with existing nonvolatile memory is related to greater non-volatility of CPU for electronics and other storage devices. Furthermore, use of this new CAM enables the development of electronics that start instantly and consume zero electricity while in standby mode.
Key features of these newly developed technologies are as follows:
- High-speed data retrieval
In order for CAM to be both nonvolatile and maintain a high speed, two spintronics devices, spinning in opposite directions to one another, were connected within the same cell. In terms of constructing the circuit, writing is done once by connecting two devices in a series using recently developed three pin particles that separate the current path into writing and reading.
This new process enables cells to become more compact since the number of writing switches per element is reduced by one. Moreover, the new CAM achieve the same level of high-speed data retrieval as current CMOS based CAM that feature 5ns and low power consumption of 9.4mW.
- Approximately half the circuit area in comparison to existing technologies
In addition to the vertical domain wall element can connect in series by separating the route of current into reading and writing, the newly developed CAM circuit technologies can reduce the number of transistors from eight to three in every two cells by sharing transistors. This results in a 50% CAM area reduction.
NEC developed nonvolatile particles aiming for both greater convenience and energy savings. Additionally, NEC and Tohoku University developed a simulation technology for a circuit diagram including spintronics particles in parallel with designing technologies for massively large integrated circuits for developments involving the most advanced spintronics logic integrated circuits.
NEC and Tohoku University will announce their latest results on June 17 at VLSI Circuit Symposium 2011 (June 13-17, Kyoto).